blob: 31ba1177ac723a75afc15dcbf5f7becada43c554 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__ASM_PTRACE_H
20#define _UAPI__ASM_PTRACE_H
21#include <linux/types.h>
22#include <asm/hwcap.h>
Christopher Ferrisd842e432019-03-07 10:21:59 -080023#include <asm/sve_context.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070024#define PSR_MODE_EL0t 0x00000000
25#define PSR_MODE_EL1t 0x00000004
26#define PSR_MODE_EL1h 0x00000005
27#define PSR_MODE_EL2t 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -070028#define PSR_MODE_EL2h 0x00000009
29#define PSR_MODE_EL3t 0x0000000c
30#define PSR_MODE_EL3h 0x0000000d
31#define PSR_MODE_MASK 0x0000000f
Ben Cheng655a7c02013-10-16 16:09:24 -070032#define PSR_MODE32_BIT 0x00000010
33#define PSR_F_BIT 0x00000040
34#define PSR_I_BIT 0x00000080
35#define PSR_A_BIT 0x00000100
Ben Cheng655a7c02013-10-16 16:09:24 -070036#define PSR_D_BIT 0x00000200
Christopher Ferris8177cdf2020-08-03 11:53:55 -070037#define PSR_BTYPE_MASK 0x00000c00
Christopher Ferris86a48372019-01-10 14:14:59 -080038#define PSR_SSBS_BIT 0x00001000
Christopher Ferris05d08e92016-02-04 13:16:38 -080039#define PSR_PAN_BIT 0x00400000
Christopher Ferris106b3a82016-08-24 12:15:38 -070040#define PSR_UAO_BIT 0x00800000
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -070041#define PSR_DIT_BIT 0x01000000
Christopher Ferris106b3a82016-08-24 12:15:38 -070042#define PSR_V_BIT 0x10000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080043#define PSR_C_BIT 0x20000000
Ben Cheng655a7c02013-10-16 16:09:24 -070044#define PSR_Z_BIT 0x40000000
45#define PSR_N_BIT 0x80000000
Christopher Ferris8177cdf2020-08-03 11:53:55 -070046#define PSR_BTYPE_SHIFT 10
Christopher Ferris106b3a82016-08-24 12:15:38 -070047#define PSR_f 0xff000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080048#define PSR_s 0x00ff0000
Ben Cheng655a7c02013-10-16 16:09:24 -070049#define PSR_x 0x0000ff00
50#define PSR_c 0x000000ff
Christopher Ferris8177cdf2020-08-03 11:53:55 -070051#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
52#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
53#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
54#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
Christopher Ferrisb8a95e22019-10-02 18:29:20 -070055#define PTRACE_SYSEMU 31
56#define PTRACE_SYSEMU_SINGLESTEP 32
Christopher Ferris106b3a82016-08-24 12:15:38 -070057#ifndef __ASSEMBLY__
Christopher Ferris05d08e92016-02-04 13:16:38 -080058struct user_pt_regs {
Tao Baod7db5942015-01-28 10:07:51 -080059 __u64 regs[31];
60 __u64 sp;
Christopher Ferris106b3a82016-08-24 12:15:38 -070061 __u64 pc;
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 __u64 pstate;
Ben Cheng655a7c02013-10-16 16:09:24 -070063};
64struct user_fpsimd_state {
Christopher Ferris106b3a82016-08-24 12:15:38 -070065 __uint128_t vregs[32];
Christopher Ferris05d08e92016-02-04 13:16:38 -080066 __u32 fpsr;
Tao Baod7db5942015-01-28 10:07:51 -080067 __u32 fpcr;
Christopher Ferris351a7962017-01-27 10:49:48 -080068 __u32 __reserved[2];
Christopher Ferris351a7962017-01-27 10:49:48 -080069};
Christopher Ferris106b3a82016-08-24 12:15:38 -070070struct user_hwdebug_state {
Christopher Ferris05d08e92016-02-04 13:16:38 -080071 __u32 dbg_info;
Tao Baod7db5942015-01-28 10:07:51 -080072 __u32 pad;
Christopher Ferris351a7962017-01-27 10:49:48 -080073 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -070074 __u64 addr;
Christopher Ferris05d08e92016-02-04 13:16:38 -080075 __u32 ctrl;
Tao Baod7db5942015-01-28 10:07:51 -080076 __u32 pad;
Christopher Ferris351a7962017-01-27 10:49:48 -080077 } dbg_regs[16];
Christopher Ferris106b3a82016-08-24 12:15:38 -070078};
Christopher Ferris934ec942018-01-31 15:29:16 -080079struct user_sve_header {
80 __u32 size;
81 __u32 max_size;
82 __u16 vl;
83 __u16 max_vl;
84 __u16 flags;
85 __u16 __reserved;
86};
87#define SVE_PT_REGS_MASK (1 << 0)
88#define SVE_PT_REGS_FPSIMD 0
89#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -070090#define SVE_PT_VL_INHERIT ((1 << 17) >> 16)
91#define SVE_PT_VL_ONEXEC ((1 << 18) >> 16)
Christopher Ferrisd842e432019-03-07 10:21:59 -080092#define SVE_PT_REGS_OFFSET ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
Christopher Ferris934ec942018-01-31 15:29:16 -080093#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
94#define SVE_PT_FPSIMD_SIZE(vq,flags) (sizeof(struct user_fpsimd_state))
Christopher Ferrisd842e432019-03-07 10:21:59 -080095#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
96#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
97#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
Christopher Ferris934ec942018-01-31 15:29:16 -080098#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
99#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
Christopher Ferris934ec942018-01-31 15:29:16 -0800100#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
Christopher Ferrisd842e432019-03-07 10:21:59 -0800101#define SVE_PT_SVE_ZREGS_OFFSET (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
102#define SVE_PT_SVE_ZREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
103#define SVE_PT_SVE_ZREGS_SIZE(vq) (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
104#define SVE_PT_SVE_PREGS_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
105#define SVE_PT_SVE_PREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
106#define SVE_PT_SVE_PREGS_SIZE(vq) (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - SVE_PT_SVE_PREGS_OFFSET(vq))
107#define SVE_PT_SVE_FFR_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
108#define SVE_PT_SVE_FPSR_OFFSET(vq) ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
Christopher Ferris934ec942018-01-31 15:29:16 -0800109#define SVE_PT_SVE_FPCR_OFFSET(vq) (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
Christopher Ferrisd842e432019-03-07 10:21:59 -0800110#define SVE_PT_SVE_SIZE(vq,flags) ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE - SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
Christopher Ferris934ec942018-01-31 15:29:16 -0800111#define SVE_PT_SIZE(vq,flags) (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) : SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
Christopher Ferrisd842e432019-03-07 10:21:59 -0800112struct user_pac_mask {
113 __u64 data_mask;
114 __u64 insn_mask;
115};
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700116struct user_pac_address_keys {
117 __uint128_t apiakey;
118 __uint128_t apibkey;
119 __uint128_t apdakey;
120 __uint128_t apdbkey;
121};
122struct user_pac_generic_keys {
123 __uint128_t apgakey;
124};
Ben Cheng655a7c02013-10-16 16:09:24 -0700125#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800126#endif