blob: 473c5f2fa62a26a13ad19e2506987236429a018a [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferris106b3a82016-08-24 12:15:38 -07007#ifndef _UAPI_VC4_DRM_H_
8#define _UAPI_VC4_DRM_H_
9#include "drm.h"
10#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080011extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070012#endif
13#define DRM_VC4_SUBMIT_CL 0x00
14#define DRM_VC4_WAIT_SEQNO 0x01
15#define DRM_VC4_WAIT_BO 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070016#define DRM_VC4_CREATE_BO 0x03
17#define DRM_VC4_MMAP_BO 0x04
18#define DRM_VC4_CREATE_SHADER_BO 0x05
19#define DRM_VC4_GET_HANG_STATE 0x06
Christopher Ferris49f525c2016-12-12 14:55:36 -080020#define DRM_VC4_GET_PARAM 0x07
Christopher Ferris1308ad32017-11-14 17:32:13 -080021#define DRM_VC4_SET_TILING 0x08
22#define DRM_VC4_GET_TILING 0x09
23#define DRM_VC4_LABEL_BO 0x0a
Christopher Ferris934ec942018-01-31 15:29:16 -080024#define DRM_VC4_GEM_MADVISE 0x0b
Christopher Ferris76a1d452018-06-27 14:12:29 -070025#define DRM_VC4_PERFMON_CREATE 0x0c
26#define DRM_VC4_PERFMON_DESTROY 0x0d
27#define DRM_VC4_PERFMON_GET_VALUES 0x0e
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
29#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
30#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
Christopher Ferris49f525c2016-12-12 14:55:36 -080031#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
33#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
34#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
Christopher Ferris49f525c2016-12-12 14:55:36 -080035#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
Christopher Ferris1308ad32017-11-14 17:32:13 -080036#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
37#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
38#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
Christopher Ferris934ec942018-01-31 15:29:16 -080039#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
Christopher Ferris76a1d452018-06-27 14:12:29 -070040#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
41#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
42#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
Christopher Ferris49f525c2016-12-12 14:55:36 -080043struct drm_vc4_submit_rcl_surface {
Christopher Ferris106b3a82016-08-24 12:15:38 -070044 __u32 hindex;
45 __u32 offset;
46 __u16 bits;
47#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -070048 __u16 flags;
49};
50struct drm_vc4_submit_cl {
51 __u64 bin_cl;
Christopher Ferris106b3a82016-08-24 12:15:38 -070052 __u64 shader_rec;
53 __u64 uniforms;
54 __u64 bo_handles;
55 __u32 bin_cl_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -070056 __u32 shader_rec_size;
57 __u32 shader_rec_count;
58 __u32 uniforms_size;
59 __u32 bo_handle_count;
Christopher Ferris106b3a82016-08-24 12:15:38 -070060 __u16 width;
61 __u16 height;
62 __u8 min_x_tile;
63 __u8 min_y_tile;
Christopher Ferris106b3a82016-08-24 12:15:38 -070064 __u8 max_x_tile;
65 __u8 max_y_tile;
66 struct drm_vc4_submit_rcl_surface color_read;
67 struct drm_vc4_submit_rcl_surface color_write;
Christopher Ferris106b3a82016-08-24 12:15:38 -070068 struct drm_vc4_submit_rcl_surface zs_read;
69 struct drm_vc4_submit_rcl_surface zs_write;
70 struct drm_vc4_submit_rcl_surface msaa_color_write;
71 struct drm_vc4_submit_rcl_surface msaa_zs_write;
Christopher Ferris106b3a82016-08-24 12:15:38 -070072 __u32 clear_color[2];
73 __u32 clear_z;
74 __u8 clear_s;
75 __u32 pad : 24;
Christopher Ferris106b3a82016-08-24 12:15:38 -070076#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
Christopher Ferris1308ad32017-11-14 17:32:13 -080077#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
78#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
79#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
Christopher Ferris106b3a82016-08-24 12:15:38 -070080 __u32 flags;
81 __u64 seqno;
Christopher Ferris76a1d452018-06-27 14:12:29 -070082 __u32 perfmonid;
Christopher Ferris9ce28842018-10-25 12:11:39 -070083 __u32 in_sync;
84 __u32 out_sync;
Christopher Ferris76a1d452018-06-27 14:12:29 -070085 __u32 pad2;
Christopher Ferris106b3a82016-08-24 12:15:38 -070086};
Christopher Ferris106b3a82016-08-24 12:15:38 -070087struct drm_vc4_wait_seqno {
88 __u64 seqno;
89 __u64 timeout_ns;
90};
Christopher Ferris106b3a82016-08-24 12:15:38 -070091struct drm_vc4_wait_bo {
92 __u32 handle;
93 __u32 pad;
94 __u64 timeout_ns;
Christopher Ferris106b3a82016-08-24 12:15:38 -070095};
96struct drm_vc4_create_bo {
97 __u32 size;
98 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -070099 __u32 handle;
100 __u32 pad;
101};
102struct drm_vc4_mmap_bo {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700103 __u32 handle;
104 __u32 flags;
105 __u64 offset;
106};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700107struct drm_vc4_create_shader_bo {
108 __u32 size;
109 __u32 flags;
110 __u64 data;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700111 __u32 handle;
112 __u32 pad;
113};
114struct drm_vc4_get_hang_state_bo {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700115 __u32 handle;
116 __u32 paddr;
117 __u32 size;
118 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700119};
120struct drm_vc4_get_hang_state {
121 __u64 bo;
122 __u32 bo_count;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700123 __u32 start_bin, start_render;
124 __u32 ct0ca, ct0ea;
125 __u32 ct1ca, ct1ea;
126 __u32 ct0cs, ct1cs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127 __u32 ct0ra0, ct1ra0;
128 __u32 bpca, bpcs;
129 __u32 bpoa, bpos;
130 __u32 vpmbase;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700131 __u32 dbge;
132 __u32 fdbgo;
133 __u32 fdbgb;
134 __u32 fdbgr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700135 __u32 fdbgs;
136 __u32 errstat;
137 __u32 pad[16];
138};
Christopher Ferris49f525c2016-12-12 14:55:36 -0800139#define DRM_VC4_PARAM_V3D_IDENT0 0
140#define DRM_VC4_PARAM_V3D_IDENT1 1
Christopher Ferris49f525c2016-12-12 14:55:36 -0800141#define DRM_VC4_PARAM_V3D_IDENT2 2
142#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800143#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
144#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
Christopher Ferris1308ad32017-11-14 17:32:13 -0800145#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
Christopher Ferris934ec942018-01-31 15:29:16 -0800146#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7
Christopher Ferris76a1d452018-06-27 14:12:29 -0700147#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8
Christopher Ferris49f525c2016-12-12 14:55:36 -0800148struct drm_vc4_get_param {
149 __u32 param;
Christopher Ferris49f525c2016-12-12 14:55:36 -0800150 __u32 pad;
151 __u64 value;
152};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800153struct drm_vc4_get_tiling {
154 __u32 handle;
155 __u32 flags;
156 __u64 modifier;
157};
158struct drm_vc4_set_tiling {
159 __u32 handle;
160 __u32 flags;
161 __u64 modifier;
162};
163struct drm_vc4_label_bo {
164 __u32 handle;
165 __u32 len;
166 __u64 name;
167};
Christopher Ferris934ec942018-01-31 15:29:16 -0800168#define VC4_MADV_WILLNEED 0
169#define VC4_MADV_DONTNEED 1
170#define __VC4_MADV_PURGED 2
171#define __VC4_MADV_NOTSUPP 3
172struct drm_vc4_gem_madvise {
173 __u32 handle;
174 __u32 madv;
175 __u32 retained;
176 __u32 pad;
177};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700178enum {
179 VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
180 VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
181 VC4_PERFCNT_FEP_CLIPPED_QUADS,
182 VC4_PERFCNT_FEP_VALID_QUADS,
183 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
184 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
185 VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
186 VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
187 VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
188 VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
189 VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
190 VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
191 VC4_PERFCNT_PSE_PRIMS_REVERSED,
192 VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
193 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
194 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
195 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
196 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
197 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
198 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
199 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
200 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
201 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
202 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
203 VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
204 VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
205 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
206 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
207 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
208 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
209 VC4_PERFCNT_NUM_EVENTS,
210};
211#define DRM_VC4_MAX_PERF_COUNTERS 16
212struct drm_vc4_perfmon_create {
213 __u32 id;
214 __u32 ncounters;
215 __u8 events[DRM_VC4_MAX_PERF_COUNTERS];
216};
217struct drm_vc4_perfmon_destroy {
218 __u32 id;
219};
220struct drm_vc4_perfmon_get_values {
221 __u32 id;
222 __u64 values_ptr;
223};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700224#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800225}
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800226#endif
227#endif