blob: 9ef645a101daa2731f29916335811ea0acd0cf85 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _VIA_DRM_H_
20#define _VIA_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
Ben Cheng655a7c02013-10-16 16:09:24 -070025#ifndef _VIA_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define _VIA_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define VIA_NR_SAREA_CLIPRECTS 8
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#define VIA_NR_XVMC_PORTS 10
Ben Cheng655a7c02013-10-16 16:09:24 -070029#define VIA_NR_XVMC_LOCKS 5
30#define VIA_MAX_CACHELINE_SIZE 64
Tao Baod7db5942015-01-28 10:07:51 -080031#define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo)))
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define VIA_NR_TEX_REGIONS 64
Ben Cheng655a7c02013-10-16 16:09:24 -070033#define VIA_LOG_MIN_TEX_REGION_SIZE 16
34#endif
35#define VIA_UPLOAD_TEX0IMAGE 0x1
Christopher Ferris106b3a82016-08-24 12:15:38 -070036#define VIA_UPLOAD_TEX1IMAGE 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -070037#define VIA_UPLOAD_CTX 0x4
38#define VIA_UPLOAD_BUFFERS 0x8
39#define VIA_UPLOAD_TEX0 0x10
Christopher Ferris106b3a82016-08-24 12:15:38 -070040#define VIA_UPLOAD_TEX1 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -070041#define VIA_UPLOAD_CLIPRECTS 0x40
42#define VIA_UPLOAD_ALL 0xff
43#define DRM_VIA_ALLOCMEM 0x00
Christopher Ferris106b3a82016-08-24 12:15:38 -070044#define DRM_VIA_FREEMEM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -070045#define DRM_VIA_AGP_INIT 0x02
46#define DRM_VIA_FB_INIT 0x03
47#define DRM_VIA_MAP_INIT 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -070048#define DRM_VIA_DEC_FUTEX 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -070049#define NOT_USED
50#define DRM_VIA_DMA_INIT 0x07
51#define DRM_VIA_CMDBUFFER 0x08
Christopher Ferris106b3a82016-08-24 12:15:38 -070052#define DRM_VIA_FLUSH 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -070053#define DRM_VIA_PCICMD 0x0a
54#define DRM_VIA_CMDBUF_SIZE 0x0b
55#define NOT_USED
Christopher Ferris106b3a82016-08-24 12:15:38 -070056#define DRM_VIA_WAIT_IRQ 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -070057#define DRM_VIA_DMA_BLIT 0x0e
58#define DRM_VIA_BLIT_SYNC 0x0f
59#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -070060#define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
Ben Cheng655a7c02013-10-16 16:09:24 -070061#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
62#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
63#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -070064#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
Ben Cheng655a7c02013-10-16 16:09:24 -070065#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
Tao Baod7db5942015-01-28 10:07:51 -080066#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
67#define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH)
Christopher Ferris106b3a82016-08-24 12:15:38 -070068#define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
Tao Baod7db5942015-01-28 10:07:51 -080069#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t)
70#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
Ben Cheng655a7c02013-10-16 16:09:24 -070071#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -070072#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
Ben Cheng655a7c02013-10-16 16:09:24 -070073#define VIA_TEX_SETUP_SIZE 8
74#define VIA_FRONT 0x1
75#define VIA_BACK 0x2
Christopher Ferris106b3a82016-08-24 12:15:38 -070076#define VIA_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070077#define VIA_STENCIL 0x8
78#define VIA_MEM_VIDEO 0
79#define VIA_MEM_AGP 1
Christopher Ferris106b3a82016-08-24 12:15:38 -070080#define VIA_MEM_SYSTEM 2
Ben Cheng655a7c02013-10-16 16:09:24 -070081#define VIA_MEM_MIXED 3
82#define VIA_MEM_UNKNOWN 4
83typedef struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -070084 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -080085 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -070086} drm_via_agp_t;
87typedef struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -070088 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -080089 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -070090} drm_via_fb_t;
91typedef struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -070092 __u32 context;
Tao Baod7db5942015-01-28 10:07:51 -080093 __u32 type;
94 __u32 size;
95 unsigned long index;
Christopher Ferris106b3a82016-08-24 12:15:38 -070096 unsigned long offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070097} drm_via_mem_t;
98typedef struct _drm_via_init {
Tao Baod7db5942015-01-28 10:07:51 -080099 enum {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700100 VIA_INIT_MAP = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800101 VIA_CLEANUP_MAP = 0x02
102 } func;
103 unsigned long sarea_priv_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700104 unsigned long fb_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800105 unsigned long mmio_offset;
106 unsigned long agpAddr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700107} drm_via_init_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700108typedef struct _drm_via_futex {
Tao Baod7db5942015-01-28 10:07:51 -0800109 enum {
110 VIA_FUTEX_WAIT = 0x00,
111 VIA_FUTEX_WAKE = 0X01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700112 } func;
Tao Baod7db5942015-01-28 10:07:51 -0800113 __u32 ms;
114 __u32 lock;
115 __u32 val;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700116} drm_via_futex_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700117typedef struct _drm_via_dma_init {
Tao Baod7db5942015-01-28 10:07:51 -0800118 enum {
119 VIA_INIT_DMA = 0x01,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700120 VIA_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800121 VIA_DMA_INITIALIZED = 0x03
122 } func;
123 unsigned long offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700124 unsigned long size;
Tao Baod7db5942015-01-28 10:07:51 -0800125 unsigned long reg_pause_addr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700126} drm_via_dma_init_t;
127typedef struct _drm_via_cmdbuffer {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700128 char __user * buf;
Tao Baod7db5942015-01-28 10:07:51 -0800129 unsigned long size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700130} drm_via_cmdbuffer_t;
131typedef struct _drm_via_tex_region {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700132 unsigned char next, prev;
Tao Baod7db5942015-01-28 10:07:51 -0800133 unsigned char inUse;
134 int age;
Ben Cheng655a7c02013-10-16 16:09:24 -0700135} drm_via_tex_region_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700136typedef struct _drm_via_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800137 unsigned int dirty;
138 unsigned int nbox;
139 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700140 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
Tao Baod7db5942015-01-28 10:07:51 -0800141 int texAge;
142 int ctxOwner;
143 int vertexPrim;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700144 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
Tao Baod7db5942015-01-28 10:07:51 -0800145 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
146 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
147 unsigned int XvMCCtxNoGrabbed;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700148 unsigned int pfCurrentOffset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700149} drm_via_sarea_t;
150typedef struct _drm_via_cmdbuf_size {
Tao Baod7db5942015-01-28 10:07:51 -0800151 enum {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700152 VIA_CMDBUF_SPACE = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800153 VIA_CMDBUF_LAG = 0x02
154 } func;
155 int wait;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700156 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700157} drm_via_cmdbuf_size_t;
158typedef enum {
Tao Baod7db5942015-01-28 10:07:51 -0800159 VIA_IRQ_ABSOLUTE = 0x0,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700160 VIA_IRQ_RELATIVE = 0x1,
Tao Baod7db5942015-01-28 10:07:51 -0800161 VIA_IRQ_SIGNAL = 0x10000000,
162 VIA_IRQ_FORCE_SEQUENCE = 0x20000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700163} via_irq_seq_type_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700164#define VIA_IRQ_FLAGS_MASK 0xF0000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700165enum drm_via_irqs {
Tao Baod7db5942015-01-28 10:07:51 -0800166 drm_via_irq_hqv0 = 0,
167 drm_via_irq_hqv1,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700168 drm_via_irq_dma0_dd,
Tao Baod7db5942015-01-28 10:07:51 -0800169 drm_via_irq_dma0_td,
170 drm_via_irq_dma1_dd,
171 drm_via_irq_dma1_td,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700172 drm_via_irq_num
Ben Cheng655a7c02013-10-16 16:09:24 -0700173};
174struct drm_via_wait_irq_request {
Tao Baod7db5942015-01-28 10:07:51 -0800175 unsigned irq;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700176 via_irq_seq_type_t type;
Tao Baod7db5942015-01-28 10:07:51 -0800177 __u32 sequence;
178 __u32 signal;
Ben Cheng655a7c02013-10-16 16:09:24 -0700179};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700180typedef union drm_via_irqwait {
Tao Baod7db5942015-01-28 10:07:51 -0800181 struct drm_via_wait_irq_request request;
182 struct drm_wait_vblank_reply reply;
Ben Cheng655a7c02013-10-16 16:09:24 -0700183} drm_via_irqwait_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700184typedef struct drm_via_blitsync {
Tao Baod7db5942015-01-28 10:07:51 -0800185 __u32 sync_handle;
186 unsigned engine;
Ben Cheng655a7c02013-10-16 16:09:24 -0700187} drm_via_blitsync_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700188typedef struct drm_via_dmablit {
Tao Baod7db5942015-01-28 10:07:51 -0800189 __u32 num_lines;
190 __u32 line_length;
191 __u32 fb_addr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700192 __u32 fb_stride;
Tao Baod7db5942015-01-28 10:07:51 -0800193 unsigned char * mem_addr;
194 __u32 mem_stride;
195 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700196 int to_fb;
Tao Baod7db5942015-01-28 10:07:51 -0800197 drm_via_blitsync_t sync;
Ben Cheng655a7c02013-10-16 16:09:24 -0700198} drm_via_dmablit_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700199#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800200}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700201#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700202#endif