Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef _VIA_DRM_H_ |
| 20 | #define _VIA_DRM_H_ |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 21 | #include "drm.h" |
| 22 | #ifdef __cplusplus |
Christopher Ferris | 48fe0ae | 2019-01-10 15:59:33 -0800 | [diff] [blame^] | 23 | extern "C" { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 24 | #endif |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 25 | #ifndef _VIA_DEFINES_ |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 26 | #define _VIA_DEFINES_ |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 27 | #define VIA_NR_SAREA_CLIPRECTS 8 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 28 | #define VIA_NR_XVMC_PORTS 10 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 29 | #define VIA_NR_XVMC_LOCKS 5 |
| 30 | #define VIA_MAX_CACHELINE_SIZE 64 |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 31 | #define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo))) |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 32 | #define VIA_NR_TEX_REGIONS 64 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 33 | #define VIA_LOG_MIN_TEX_REGION_SIZE 16 |
| 34 | #endif |
| 35 | #define VIA_UPLOAD_TEX0IMAGE 0x1 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 36 | #define VIA_UPLOAD_TEX1IMAGE 0x2 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 37 | #define VIA_UPLOAD_CTX 0x4 |
| 38 | #define VIA_UPLOAD_BUFFERS 0x8 |
| 39 | #define VIA_UPLOAD_TEX0 0x10 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 40 | #define VIA_UPLOAD_TEX1 0x20 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 41 | #define VIA_UPLOAD_CLIPRECTS 0x40 |
| 42 | #define VIA_UPLOAD_ALL 0xff |
| 43 | #define DRM_VIA_ALLOCMEM 0x00 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 44 | #define DRM_VIA_FREEMEM 0x01 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 45 | #define DRM_VIA_AGP_INIT 0x02 |
| 46 | #define DRM_VIA_FB_INIT 0x03 |
| 47 | #define DRM_VIA_MAP_INIT 0x04 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 48 | #define DRM_VIA_DEC_FUTEX 0x05 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 49 | #define NOT_USED |
| 50 | #define DRM_VIA_DMA_INIT 0x07 |
| 51 | #define DRM_VIA_CMDBUFFER 0x08 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 52 | #define DRM_VIA_FLUSH 0x09 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 53 | #define DRM_VIA_PCICMD 0x0a |
| 54 | #define DRM_VIA_CMDBUF_SIZE 0x0b |
| 55 | #define NOT_USED |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 56 | #define DRM_VIA_WAIT_IRQ 0x0d |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 57 | #define DRM_VIA_DMA_BLIT 0x0e |
| 58 | #define DRM_VIA_BLIT_SYNC 0x0f |
| 59 | #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 60 | #define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 61 | #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) |
| 62 | #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) |
| 63 | #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 64 | #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 65 | #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 66 | #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) |
| 67 | #define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH) |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 68 | #define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 69 | #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t) |
| 70 | #define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 71 | #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 72 | #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 73 | #define VIA_TEX_SETUP_SIZE 8 |
| 74 | #define VIA_FRONT 0x1 |
| 75 | #define VIA_BACK 0x2 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 76 | #define VIA_DEPTH 0x4 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 77 | #define VIA_STENCIL 0x8 |
| 78 | #define VIA_MEM_VIDEO 0 |
| 79 | #define VIA_MEM_AGP 1 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 80 | #define VIA_MEM_SYSTEM 2 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 81 | #define VIA_MEM_MIXED 3 |
| 82 | #define VIA_MEM_UNKNOWN 4 |
| 83 | typedef struct { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 84 | __u32 offset; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 85 | __u32 size; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 86 | } drm_via_agp_t; |
| 87 | typedef struct { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 88 | __u32 offset; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 89 | __u32 size; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 90 | } drm_via_fb_t; |
| 91 | typedef struct { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 92 | __u32 context; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 93 | __u32 type; |
| 94 | __u32 size; |
| 95 | unsigned long index; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 96 | unsigned long offset; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 97 | } drm_via_mem_t; |
| 98 | typedef struct _drm_via_init { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 99 | enum { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 100 | VIA_INIT_MAP = 0x01, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 101 | VIA_CLEANUP_MAP = 0x02 |
| 102 | } func; |
| 103 | unsigned long sarea_priv_offset; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 104 | unsigned long fb_offset; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 105 | unsigned long mmio_offset; |
| 106 | unsigned long agpAddr; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 107 | } drm_via_init_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 108 | typedef struct _drm_via_futex { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 109 | enum { |
| 110 | VIA_FUTEX_WAIT = 0x00, |
| 111 | VIA_FUTEX_WAKE = 0X01 |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 112 | } func; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 113 | __u32 ms; |
| 114 | __u32 lock; |
| 115 | __u32 val; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 116 | } drm_via_futex_t; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 117 | typedef struct _drm_via_dma_init { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 118 | enum { |
| 119 | VIA_INIT_DMA = 0x01, |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 120 | VIA_CLEANUP_DMA = 0x02, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 121 | VIA_DMA_INITIALIZED = 0x03 |
| 122 | } func; |
| 123 | unsigned long offset; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 124 | unsigned long size; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 125 | unsigned long reg_pause_addr; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 126 | } drm_via_dma_init_t; |
| 127 | typedef struct _drm_via_cmdbuffer { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 128 | char __user * buf; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 129 | unsigned long size; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 130 | } drm_via_cmdbuffer_t; |
| 131 | typedef struct _drm_via_tex_region { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 132 | unsigned char next, prev; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 133 | unsigned char inUse; |
| 134 | int age; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 135 | } drm_via_tex_region_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 136 | typedef struct _drm_via_sarea { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 137 | unsigned int dirty; |
| 138 | unsigned int nbox; |
| 139 | struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 140 | drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 141 | int texAge; |
| 142 | int ctxOwner; |
| 143 | int vertexPrim; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 144 | char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 145 | unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; |
| 146 | unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; |
| 147 | unsigned int XvMCCtxNoGrabbed; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 148 | unsigned int pfCurrentOffset; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 149 | } drm_via_sarea_t; |
| 150 | typedef struct _drm_via_cmdbuf_size { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 151 | enum { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 152 | VIA_CMDBUF_SPACE = 0x01, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 153 | VIA_CMDBUF_LAG = 0x02 |
| 154 | } func; |
| 155 | int wait; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 156 | __u32 size; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 157 | } drm_via_cmdbuf_size_t; |
| 158 | typedef enum { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 159 | VIA_IRQ_ABSOLUTE = 0x0, |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 160 | VIA_IRQ_RELATIVE = 0x1, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 161 | VIA_IRQ_SIGNAL = 0x10000000, |
| 162 | VIA_IRQ_FORCE_SEQUENCE = 0x20000000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 163 | } via_irq_seq_type_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 164 | #define VIA_IRQ_FLAGS_MASK 0xF0000000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 165 | enum drm_via_irqs { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 166 | drm_via_irq_hqv0 = 0, |
| 167 | drm_via_irq_hqv1, |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 168 | drm_via_irq_dma0_dd, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 169 | drm_via_irq_dma0_td, |
| 170 | drm_via_irq_dma1_dd, |
| 171 | drm_via_irq_dma1_td, |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 172 | drm_via_irq_num |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 173 | }; |
| 174 | struct drm_via_wait_irq_request { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 175 | unsigned irq; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 176 | via_irq_seq_type_t type; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 177 | __u32 sequence; |
| 178 | __u32 signal; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 179 | }; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 180 | typedef union drm_via_irqwait { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 181 | struct drm_via_wait_irq_request request; |
| 182 | struct drm_wait_vblank_reply reply; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 183 | } drm_via_irqwait_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 184 | typedef struct drm_via_blitsync { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 185 | __u32 sync_handle; |
| 186 | unsigned engine; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 187 | } drm_via_blitsync_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 188 | typedef struct drm_via_dmablit { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 189 | __u32 num_lines; |
| 190 | __u32 line_length; |
| 191 | __u32 fb_addr; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 192 | __u32 fb_stride; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 193 | unsigned char * mem_addr; |
| 194 | __u32 mem_stride; |
| 195 | __u32 flags; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 196 | int to_fb; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 197 | drm_via_blitsync_t sync; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 198 | } drm_via_dmablit_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 199 | #ifdef __cplusplus |
Christopher Ferris | 48fe0ae | 2019-01-10 15:59:33 -0800 | [diff] [blame^] | 200 | } |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 201 | #endif |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 202 | #endif |