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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / via_drm.h
blob: 1eb334e54c47dfffaecaeab99d3d12a7cd03c96b [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _VIA_DRM_H_
20#define _VIA_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]21#include "drm.h"
22#ifdef __cplusplus
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25#ifndef _VIA_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26#define _VIA_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27#define VIA_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]29#define VIA_NR_XVMC_PORTS 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30#define VIA_NR_XVMC_LOCKS 5
31#define VIA_MAX_CACHELINE_SIZE 64
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]32#define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo)))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]34#define VIA_NR_TEX_REGIONS 64
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35#define VIA_LOG_MIN_TEX_REGION_SIZE 16
36#endif
37#define VIA_UPLOAD_TEX0IMAGE 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]39#define VIA_UPLOAD_TEX1IMAGE 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40#define VIA_UPLOAD_CTX 0x4
41#define VIA_UPLOAD_BUFFERS 0x8
42#define VIA_UPLOAD_TEX0 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]44#define VIA_UPLOAD_TEX1 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]45#define VIA_UPLOAD_CLIPRECTS 0x40
46#define VIA_UPLOAD_ALL 0xff
47#define DRM_VIA_ALLOCMEM 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]49#define DRM_VIA_FREEMEM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50#define DRM_VIA_AGP_INIT 0x02
51#define DRM_VIA_FB_INIT 0x03
52#define DRM_VIA_MAP_INIT 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]54#define DRM_VIA_DEC_FUTEX 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]55#define NOT_USED
56#define DRM_VIA_DMA_INIT 0x07
57#define DRM_VIA_CMDBUFFER 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]59#define DRM_VIA_FLUSH 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]60#define DRM_VIA_PCICMD 0x0a
61#define DRM_VIA_CMDBUF_SIZE 0x0b
62#define NOT_USED
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]64#define DRM_VIA_WAIT_IRQ 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65#define DRM_VIA_DMA_BLIT 0x0e
66#define DRM_VIA_BLIT_SYNC 0x0f
67#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]69#define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]70#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
71#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
72#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]74#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]76#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
77#define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]79#define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]80#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t)
81#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]84#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85#define VIA_TEX_SETUP_SIZE 8
86#define VIA_FRONT 0x1
87#define VIA_BACK 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]89#define VIA_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90#define VIA_STENCIL 0x8
91#define VIA_MEM_VIDEO 0
92#define VIA_MEM_AGP 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]94#define VIA_MEM_SYSTEM 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95#define VIA_MEM_MIXED 3
96#define VIA_MEM_UNKNOWN 4
97typedef struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]99 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]100 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]101} drm_via_agp_t;
102typedef struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]104 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]105 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]106} drm_via_fb_t;
107typedef struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]109 __u32 context;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 __u32 type;
111 __u32 size;
112 unsigned long index;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]114 unsigned long offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115} drm_via_mem_t;
116typedef struct _drm_via_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 enum {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]119 VIA_INIT_MAP = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]120 VIA_CLEANUP_MAP = 0x02
121 } func;
122 unsigned long sarea_priv_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]124 unsigned long fb_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]125 unsigned long mmio_offset;
126 unsigned long agpAddr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127} drm_via_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]129typedef struct _drm_via_futex {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]130 enum {
131 VIA_FUTEX_WAIT = 0x00,
132 VIA_FUTEX_WAKE = 0X01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]134 } func;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]135 __u32 ms;
136 __u32 lock;
137 __u32 val;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]139} drm_via_futex_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]140typedef struct _drm_via_dma_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]141 enum {
142 VIA_INIT_DMA = 0x01,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]144 VIA_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]145 VIA_DMA_INITIALIZED = 0x03
146 } func;
147 unsigned long offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]149 unsigned long size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]150 unsigned long reg_pause_addr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]151} drm_via_dma_init_t;
152typedef struct _drm_via_cmdbuffer {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]154 char __user * buf;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 unsigned long size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]156} drm_via_cmdbuffer_t;
157typedef struct _drm_via_tex_region {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]159 unsigned char next, prev;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]160 unsigned char inUse;
161 int age;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]162} drm_via_tex_region_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]164typedef struct _drm_via_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165 unsigned int dirty;
166 unsigned int nbox;
167 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]169 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]170 int texAge;
171 int ctxOwner;
172 int vertexPrim;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]174 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]175 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
176 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
177 unsigned int XvMCCtxNoGrabbed;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]179 unsigned int pfCurrentOffset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]180} drm_via_sarea_t;
181typedef struct _drm_via_cmdbuf_size {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]182 enum {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]184 VIA_CMDBUF_SPACE = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]185 VIA_CMDBUF_LAG = 0x02
186 } func;
187 int wait;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]189 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]190} drm_via_cmdbuf_size_t;
191typedef enum {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]192 VIA_IRQ_ABSOLUTE = 0x0,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]194 VIA_IRQ_RELATIVE = 0x1,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]195 VIA_IRQ_SIGNAL = 0x10000000,
196 VIA_IRQ_FORCE_SEQUENCE = 0x20000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197} via_irq_seq_type_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]199#define VIA_IRQ_FLAGS_MASK 0xF0000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]200enum drm_via_irqs {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]201 drm_via_irq_hqv0 = 0,
202 drm_via_irq_hqv1,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]204 drm_via_irq_dma0_dd,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]205 drm_via_irq_dma0_td,
206 drm_via_irq_dma1_dd,
207 drm_via_irq_dma1_td,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]209 drm_via_irq_num
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]210};
211struct drm_via_wait_irq_request {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]212 unsigned irq;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]214 via_irq_seq_type_t type;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]215 __u32 sequence;
216 __u32 signal;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]219typedef union drm_via_irqwait {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]220 struct drm_via_wait_irq_request request;
221 struct drm_wait_vblank_reply reply;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222} drm_via_irqwait_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]224typedef struct drm_via_blitsync {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]225 __u32 sync_handle;
226 unsigned engine;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227} drm_via_blitsync_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]229typedef struct drm_via_dmablit {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]230 __u32 num_lines;
231 __u32 line_length;
232 __u32 fb_addr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]234 __u32 fb_stride;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]235 unsigned char * mem_addr;
236 __u32 mem_stride;
237 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]239 int to_fb;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]240 drm_via_blitsync_t sync;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]241} drm_via_dmablit_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]242#ifdef __cplusplus
243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
244#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]245#endif