blob: f9c3447a4610937b1d35dcbcb8eb9c3071603917 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __NOUVEAU_DRM_H__
20#define __NOUVEAU_DRM_H__
Christopher Ferris82d75042015-01-26 10:57:07 -080021#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
Christopher Ferris106b3a82016-08-24 12:15:38 -070022#include "drm.h"
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#ifdef __cplusplus
24#endif
25#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -080026#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
28#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
Christopher Ferris05d08e92016-02-04 13:16:38 -080029#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define NOUVEAU_GEM_TILE_COMP 0x00030000
31#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
Ben Cheng655a7c02013-10-16 16:09:24 -070032#define NOUVEAU_GEM_TILE_16BPP 0x00000001
33#define NOUVEAU_GEM_TILE_32BPP 0x00000002
34#define NOUVEAU_GEM_TILE_ZETA 0x00000004
35#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -070036struct drm_nouveau_gem_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -070037 __u32 handle;
38 __u32 domain;
Christopher Ferris106b3a82016-08-24 12:15:38 -070039 __u64 size;
40 __u64 offset;
41 __u64 map_handle;
42 __u32 tile_mode;
Christopher Ferris106b3a82016-08-24 12:15:38 -070043 __u32 tile_flags;
Ben Cheng655a7c02013-10-16 16:09:24 -070044};
45struct drm_nouveau_gem_new {
Tao Baod7db5942015-01-28 10:07:51 -080046 struct drm_nouveau_gem_info info;
Christopher Ferris106b3a82016-08-24 12:15:38 -070047 __u32 channel_hint;
48 __u32 align;
Ben Cheng655a7c02013-10-16 16:09:24 -070049};
50#define NOUVEAU_GEM_MAX_BUFFERS 1024
Christopher Ferris106b3a82016-08-24 12:15:38 -070051struct drm_nouveau_gem_pushbuf_bo_presumed {
52 __u32 valid;
53 __u32 domain;
54 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070055};
Ben Cheng655a7c02013-10-16 16:09:24 -070056struct drm_nouveau_gem_pushbuf_bo {
Christopher Ferris106b3a82016-08-24 12:15:38 -070057 __u64 user_priv;
58 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070059 __u32 read_domains;
60 __u32 write_domains;
61 __u32 valid_domains;
Tao Baod7db5942015-01-28 10:07:51 -080062 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
Ben Cheng655a7c02013-10-16 16:09:24 -070063};
Ben Cheng655a7c02013-10-16 16:09:24 -070064#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
65#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
66#define NOUVEAU_GEM_RELOC_OR (1 << 2)
67#define NOUVEAU_GEM_MAX_RELOCS 1024
Ben Cheng655a7c02013-10-16 16:09:24 -070068struct drm_nouveau_gem_pushbuf_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -070069 __u32 reloc_bo_index;
70 __u32 reloc_bo_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070071 __u32 bo_index;
72 __u32 flags;
73 __u32 data;
74 __u32 vor;
Christopher Ferris106b3a82016-08-24 12:15:38 -070075 __u32 tor;
Ben Cheng655a7c02013-10-16 16:09:24 -070076};
77#define NOUVEAU_GEM_MAX_PUSH 512
78struct drm_nouveau_gem_pushbuf_push {
Christopher Ferris106b3a82016-08-24 12:15:38 -070079 __u32 bo_index;
80 __u32 pad;
81 __u64 offset;
82 __u64 length;
Ben Cheng655a7c02013-10-16 16:09:24 -070083};
Ben Cheng655a7c02013-10-16 16:09:24 -070084struct drm_nouveau_gem_pushbuf {
Christopher Ferris106b3a82016-08-24 12:15:38 -070085 __u32 channel;
86 __u32 nr_buffers;
Christopher Ferris106b3a82016-08-24 12:15:38 -070087 __u64 buffers;
88 __u32 nr_relocs;
89 __u32 nr_push;
90 __u64 relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -070091 __u64 push;
92 __u32 suffix0;
93 __u32 suffix1;
94 __u64 vram_available;
Christopher Ferris106b3a82016-08-24 12:15:38 -070095 __u64 gart_available;
Ben Cheng655a7c02013-10-16 16:09:24 -070096};
97#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
98#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
99struct drm_nouveau_gem_cpu_prep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700100 __u32 handle;
101 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700102};
103struct drm_nouveau_gem_cpu_fini {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700104 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700105};
106#define DRM_NOUVEAU_GETPARAM 0x00
107#define DRM_NOUVEAU_SETPARAM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700108#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
109#define DRM_NOUVEAU_CHANNEL_FREE 0x03
110#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
111#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700112#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
Christopher Ferris82d75042015-01-26 10:57:07 -0800113#define DRM_NOUVEAU_NVIF 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700114#define DRM_NOUVEAU_GEM_NEW 0x40
115#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
Christopher Ferris82d75042015-01-26 10:57:07 -0800116#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
Ben Cheng655a7c02013-10-16 16:09:24 -0700117#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
118#define DRM_NOUVEAU_GEM_INFO 0x44
119#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
Christopher Ferris82d75042015-01-26 10:57:07 -0800120#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
Tao Baod7db5942015-01-28 10:07:51 -0800121#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
122#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
Ben Cheng655a7c02013-10-16 16:09:24 -0700123#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700124#ifdef __cplusplus
Christopher Ferris82d75042015-01-26 10:57:07 -0800125#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700126#endif