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gerrit.omnirom.org / android_bionic / 48af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0 / . / libc / kernel / uapi / drm / i915_drm.h
blob: 94b96364ff1752219910155c0c4ecc5475db8073 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_I915_DRM_H_
20#define _UAPI_I915_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]21#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]24#endif
25#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]26#define I915_ERROR_UEVENT "ERROR"
27#define I915_RESET_UEVENT "RESET"
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]29enum i915_mocs_table_index {
30 I915_MOCS_UNCACHED,
31 I915_MOCS_PTE,
32 I915_MOCS_CACHED,
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]35#define I915_NR_TEX_REGIONS 255
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36#define I915_LOG_MIN_TEX_REGION_SIZE 14
37typedef struct _drm_i915_init {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]39 enum {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]40 I915_INIT_DMA = 0x01,
41 I915_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]42 I915_RESUME_DMA = 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]44 } func;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]45 unsigned int mmio_offset;
46 int sarea_priv_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]47 unsigned int ring_start;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]49 unsigned int ring_end;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]50 unsigned int ring_size;
51 unsigned int front_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]52 unsigned int back_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]54 unsigned int depth_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]55 unsigned int w;
56 unsigned int h;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]57 unsigned int pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]59 unsigned int pitch_bits;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]60 unsigned int back_pitch;
61 unsigned int depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]62 unsigned int cpp;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]64 unsigned int chipset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65} drm_i915_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66typedef struct _drm_i915_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]69 int last_upload;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]70 int last_enqueue;
71 int last_dispatch;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]72 int ctxOwner;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]74 int texAge;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]75 int pf_enabled;
76 int pf_active;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]77 int pf_current_page;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]79 int perf_boxes;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]80 int width, height;
81 drm_handle_t front_handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]82 int front_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]84 int front_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]85 drm_handle_t back_handle;
86 int back_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]87 int back_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]89 drm_handle_t depth_handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]90 int depth_offset;
91 int depth_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]92 drm_handle_t tex_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]94 int tex_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]95 int tex_size;
96 int log_tex_granularity;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]97 int pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]99 int rotation;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]100 int rotated_offset;
101 int rotated_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]102 int rotated_pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]104 int virtualX, virtualY;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]105 unsigned int front_tiled;
106 unsigned int back_tiled;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]107 unsigned int depth_tiled;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]109 unsigned int rotated_tiled;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 unsigned int rotated2_tiled;
111 int pipeA_x;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]112 int pipeA_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]114 int pipeA_w;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]115 int pipeA_h;
116 int pipeB_x;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 int pipeB_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]119 int pipeB_w;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]120 int pipeB_h;
121 drm_handle_t unused_handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]122 __u32 unused1, unused2, unused3;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]124 __u32 front_bo_handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]125 __u32 back_bo_handle;
126 __u32 unused_bo_handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]127 __u32 depth_bo_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]129} drm_i915_sarea_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]130#define planeA_x pipeA_x
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131#define planeA_y pipeA_y
132#define planeA_w pipeA_w
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]134#define planeA_h pipeA_h
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]135#define planeB_x pipeB_x
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]136#define planeB_y pipeB_y
137#define planeB_w pipeB_w
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]139#define planeB_h pipeB_h
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]140#define I915_BOX_RING_EMPTY 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141#define I915_BOX_FLIP 0x2
142#define I915_BOX_WAIT 0x4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]144#define I915_BOX_TEXTURE_LOAD 0x8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]145#define I915_BOX_LOST_CONTEXT 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]146#define DRM_I915_INIT 0x00
147#define DRM_I915_FLUSH 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]149#define DRM_I915_FLIP 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]150#define DRM_I915_BATCHBUFFER 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]151#define DRM_I915_IRQ_EMIT 0x04
152#define DRM_I915_IRQ_WAIT 0x05
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]154#define DRM_I915_GETPARAM 0x06
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]155#define DRM_I915_SETPARAM 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]156#define DRM_I915_ALLOC 0x08
157#define DRM_I915_FREE 0x09
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]159#define DRM_I915_INIT_HEAP 0x0a
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]160#define DRM_I915_CMDBUFFER 0x0b
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]161#define DRM_I915_DESTROY_HEAP 0x0c
162#define DRM_I915_SET_VBLANK_PIPE 0x0d
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]164#define DRM_I915_GET_VBLANK_PIPE 0x0e
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]165#define DRM_I915_VBLANK_SWAP 0x0f
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]166#define DRM_I915_HWS_ADDR 0x11
167#define DRM_I915_GEM_INIT 0x13
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]169#define DRM_I915_GEM_EXECBUFFER 0x14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]170#define DRM_I915_GEM_PIN 0x15
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]171#define DRM_I915_GEM_UNPIN 0x16
172#define DRM_I915_GEM_BUSY 0x17
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]174#define DRM_I915_GEM_THROTTLE 0x18
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]175#define DRM_I915_GEM_ENTERVT 0x19
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]176#define DRM_I915_GEM_LEAVEVT 0x1a
177#define DRM_I915_GEM_CREATE 0x1b
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]179#define DRM_I915_GEM_PREAD 0x1c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]180#define DRM_I915_GEM_PWRITE 0x1d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181#define DRM_I915_GEM_MMAP 0x1e
182#define DRM_I915_GEM_SET_DOMAIN 0x1f
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]184#define DRM_I915_GEM_SW_FINISH 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]185#define DRM_I915_GEM_SET_TILING 0x21
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]186#define DRM_I915_GEM_GET_TILING 0x22
187#define DRM_I915_GEM_GET_APERTURE 0x23
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]189#define DRM_I915_GEM_MMAP_GTT 0x24
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]190#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]191#define DRM_I915_GEM_MADVISE 0x26
192#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]194#define DRM_I915_OVERLAY_ATTRS 0x28
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]195#define DRM_I915_GEM_EXECBUFFER2 0x29
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]196#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
197#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]199#define DRM_I915_GEM_WAIT 0x2c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]200#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]201#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
202#define DRM_I915_GEM_SET_CACHING 0x2f
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]204#define DRM_I915_GEM_GET_CACHING 0x30
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]205#define DRM_I915_REG_READ 0x31
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]206#define DRM_I915_GET_RESET_STATS 0x32
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]207#define DRM_I915_GEM_USERPTR 0x33
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]209#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]210#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]211#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
212#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]214#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]215#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]217#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]219#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]220#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]221#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]222#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]224#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]225#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
226#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
227#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]229#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]230#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]231#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
232#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]234#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]235#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]236#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
237#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]239#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]240#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]241#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]242#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]244#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]245#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]246#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]247#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]249#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]250#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]251#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]252#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]254#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]255#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
256#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
257#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]259#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]260#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]261#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
262#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]264#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]265#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]266#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]267#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]269#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]270#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
271#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
272#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]274#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]275#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]276typedef struct drm_i915_batchbuffer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]277 int start;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]279 int used;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]280 int DR1;
281 int DR4;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]282 int num_cliprects;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]284 struct drm_clip_rect __user * cliprects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]285} drm_i915_batchbuffer_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]286typedef struct _drm_i915_cmdbuffer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]287 char __user * buf;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]289 int sz;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]290 int DR1;
291 int DR4;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]292 int num_cliprects;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]294 struct drm_clip_rect __user * cliprects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]295} drm_i915_cmdbuffer_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]296typedef struct drm_i915_irq_emit {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]297 int __user * irq_seq;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]299} drm_i915_irq_emit_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]300typedef struct drm_i915_irq_wait {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]301 int irq_seq;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302} drm_i915_irq_wait_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]304#define I915_PARAM_IRQ_ACTIVE 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]305#define I915_PARAM_ALLOW_BATCHBUFFER 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]306#define I915_PARAM_LAST_DISPATCH 3
307#define I915_PARAM_CHIPSET_ID 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]309#define I915_PARAM_HAS_GEM 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]310#define I915_PARAM_NUM_FENCES_AVAIL 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]311#define I915_PARAM_HAS_OVERLAY 7
312#define I915_PARAM_HAS_PAGEFLIPPING 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]314#define I915_PARAM_HAS_EXECBUF2 9
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]315#define I915_PARAM_HAS_BSD 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]316#define I915_PARAM_HAS_BLT 11
317#define I915_PARAM_HAS_RELAXED_FENCING 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]319#define I915_PARAM_HAS_COHERENT_RINGS 13
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]320#define I915_PARAM_HAS_EXEC_CONSTANTS 14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]321#define I915_PARAM_HAS_RELAXED_DELTA 15
322#define I915_PARAM_HAS_GEN7_SOL_RESET 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]324#define I915_PARAM_HAS_LLC 17
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]325#define I915_PARAM_HAS_ALIASING_PPGTT 18
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]326#define I915_PARAM_HAS_WAIT_TIMEOUT 19
327#define I915_PARAM_HAS_SEMAPHORES 20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]329#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]330#define I915_PARAM_HAS_VEBOX 22
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]331#define I915_PARAM_HAS_SECURE_BATCHES 23
332#define I915_PARAM_HAS_PINNED_BATCHES 24
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]334#define I915_PARAM_HAS_EXEC_NO_RELOC 25
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]335#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
336#define I915_PARAM_HAS_WT 27
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]337#define I915_PARAM_CMD_PARSER_VERSION 28
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]339#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]340#define I915_PARAM_MMAP_VERSION 30
341#define I915_PARAM_HAS_BSD2 31
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]342#define I915_PARAM_REVISION 32
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]344#define I915_PARAM_SUBSLICE_TOTAL 33
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]345#define I915_PARAM_EU_TOTAL 34
346#define I915_PARAM_HAS_GPU_RESET 35
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]347#define I915_PARAM_HAS_RESOURCE_STREAMER 36
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]349#define I915_PARAM_HAS_EXEC_SOFTPIN 37
Christopher Ferris49f525c2016-12-12 14:55:36 -0800[diff] [blame]350#define I915_PARAM_HAS_POOLED_EU 38
351#define I915_PARAM_MIN_EU_IN_POOL 39
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]352#define I915_PARAM_MMAP_GTT_VERSION 40
353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]354#define I915_PARAM_HAS_SCHEDULER 41
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]355typedef struct drm_i915_getparam {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]356 __s32 param;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]357 int __user * value;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]359} drm_i915_getparam_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]360#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
361#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
362#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]364#define I915_SETPARAM_NUM_USED_FENCES 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]365typedef struct drm_i915_setparam {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]366 int param;
367 int value;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]369} drm_i915_setparam_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]370#define I915_MEM_REGION_AGP 1
371typedef struct drm_i915_mem_alloc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]372 int region;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]374 int alignment;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]375 int size;
376 int __user * region_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]377} drm_i915_mem_alloc_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]379typedef struct drm_i915_mem_free {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]380 int region;
381 int region_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]382} drm_i915_mem_free_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]384typedef struct drm_i915_mem_init_heap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]385 int region;
386 int size;
387 int start;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]389} drm_i915_mem_init_heap_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]390typedef struct drm_i915_mem_destroy_heap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]391 int region;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]392} drm_i915_mem_destroy_heap_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]394#define DRM_I915_VBLANK_PIPE_A 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]395#define DRM_I915_VBLANK_PIPE_B 2
396typedef struct drm_i915_vblank_pipe {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]397 int pipe;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]399} drm_i915_vblank_pipe_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]400typedef struct drm_i915_vblank_swap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]401 drm_drawable_t drawable;
402 enum drm_vblank_seq_type seqtype;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]404 unsigned int sequence;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]405} drm_i915_vblank_swap_t;
406typedef struct drm_i915_hws_addr {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]407 __u64 addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]409} drm_i915_hws_addr_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]410struct drm_i915_gem_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]411 __u64 gtt_start;
412 __u64 gtt_end;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]414};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]415struct drm_i915_gem_create {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]416 __u64 size;
417 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]419 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]420};
421struct drm_i915_gem_pread {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]422 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]424 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]425 __u64 offset;
426 __u64 size;
427 __u64 data_ptr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]429};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]430struct drm_i915_gem_pwrite {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]431 __u32 handle;
432 __u32 pad;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]434 __u64 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]435 __u64 size;
436 __u64 data_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]437};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]439struct drm_i915_gem_mmap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]440 __u32 handle;
441 __u32 pad;
442 __u64 offset;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]444 __u64 size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]445 __u64 addr_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]446 __u64 flags;
447#define I915_MMAP_WC 0x1
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]449};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]450struct drm_i915_gem_mmap_gtt {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]451 __u32 handle;
452 __u32 pad;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]454 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]455};
456struct drm_i915_gem_set_domain {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]457 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]459 __u32 read_domains;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]460 __u32 write_domain;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]461};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]462struct drm_i915_gem_sw_finish {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]464 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]465};
466struct drm_i915_gem_relocation_entry {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]467 __u32 target_handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]469 __u32 delta;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]470 __u64 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]471 __u64 presumed_offset;
472 __u32 read_domains;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]474 __u32 write_domain;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]475};
476#define I915_GEM_DOMAIN_CPU 0x00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]477#define I915_GEM_DOMAIN_RENDER 0x00000002
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]479#define I915_GEM_DOMAIN_SAMPLER 0x00000004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]480#define I915_GEM_DOMAIN_COMMAND 0x00000008
481#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]482#define I915_GEM_DOMAIN_VERTEX 0x00000020
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]484#define I915_GEM_DOMAIN_GTT 0x00000040
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]485struct drm_i915_gem_exec_object {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]486 __u32 handle;
487 __u32 relocation_count;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]489 __u64 relocs_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]490 __u64 alignment;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]491 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]492};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]494struct drm_i915_gem_execbuffer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]495 __u64 buffers_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]496 __u32 buffer_count;
497 __u32 batch_start_offset;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]499 __u32 batch_len;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]500 __u32 DR1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]501 __u32 DR4;
502 __u32 num_cliprects;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]504 __u64 cliprects_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]505};
506struct drm_i915_gem_exec_object2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]507 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]509 __u32 relocation_count;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]510 __u64 relocs_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]511 __u64 alignment;
512 __u64 offset;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]514#define EXEC_OBJECT_NEEDS_FENCE (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]515#define EXEC_OBJECT_NEEDS_GTT (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]516#define EXEC_OBJECT_WRITE (1 << 2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]517#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800[diff] [blame]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]519#define EXEC_OBJECT_PINNED (1 << 4)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]520#define EXEC_OBJECT_PAD_TO_SIZE (1 << 5)
521#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_PAD_TO_SIZE << 1)
522 __u64 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]524 union {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]525 __u64 rsvd1;
526 __u64 pad_to_size;
527 };
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]529 __u64 rsvd2;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]530};
531struct drm_i915_gem_execbuffer2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]532 __u64 buffers_ptr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]534 __u32 buffer_count;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]535 __u32 batch_start_offset;
536 __u32 batch_len;
537 __u32 DR1;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]539 __u32 DR4;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]540 __u32 num_cliprects;
541 __u64 cliprects_ptr;
542#define I915_EXEC_RING_MASK (7 << 0)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]544#define I915_EXEC_DEFAULT (0 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]545#define I915_EXEC_RENDER (1 << 0)
546#define I915_EXEC_BSD (2 << 0)
547#define I915_EXEC_BLT (3 << 0)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]549#define I915_EXEC_VEBOX (4 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]550#define I915_EXEC_CONSTANTS_MASK (3 << 6)
551#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6)
552#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]554#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]555 __u64 flags;
556 __u64 rsvd1;
557 __u64 rsvd2;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]559};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]560#define I915_EXEC_GEN7_SOL_RESET (1 << 8)
561#define I915_EXEC_SECURE (1 << 9)
562#define I915_EXEC_IS_PINNED (1 << 10)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]564#define I915_EXEC_NO_RELOC (1 << 11)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]565#define I915_EXEC_HANDLE_LUT (1 << 12)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]566#define I915_EXEC_BSD_SHIFT (13)
567#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]569#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]570#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
571#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]572#define I915_EXEC_RESOURCE_STREAMER (1 << 15)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]574#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_RESOURCE_STREAMER << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]575#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]576#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
577#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]579struct drm_i915_gem_pin {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]580 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]581 __u32 pad;
582 __u64 alignment;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]584 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]585};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]586struct drm_i915_gem_unpin {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]587 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]589 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]590};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]591struct drm_i915_gem_busy {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]592 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]594 __u32 busy;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]595};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]596#define I915_CACHING_NONE 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]597#define I915_CACHING_CACHED 1
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]599#define I915_CACHING_DISPLAY 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]600struct drm_i915_gem_caching {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]601 __u32 handle;
602 __u32 caching;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]604};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]605#define I915_TILING_NONE 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]606#define I915_TILING_X 1
607#define I915_TILING_Y 2
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]609#define I915_TILING_LAST I915_TILING_Y
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]610#define I915_BIT_6_SWIZZLE_NONE 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]611#define I915_BIT_6_SWIZZLE_9 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]612#define I915_BIT_6_SWIZZLE_9_10 2
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]614#define I915_BIT_6_SWIZZLE_9_11 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]615#define I915_BIT_6_SWIZZLE_9_10_11 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]616#define I915_BIT_6_SWIZZLE_UNKNOWN 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]617#define I915_BIT_6_SWIZZLE_9_17 6
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]619#define I915_BIT_6_SWIZZLE_9_10_17 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]620struct drm_i915_gem_set_tiling {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]621 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]622 __u32 tiling_mode;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]624 __u32 stride;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]625 __u32 swizzle_mode;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]626};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]627struct drm_i915_gem_get_tiling {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]629 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]630 __u32 tiling_mode;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]631 __u32 swizzle_mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]632 __u32 phys_swizzle_mode;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]634};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]635struct drm_i915_gem_get_aperture {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]636 __u64 aper_size;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]637 __u64 aper_available_size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]639};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]640struct drm_i915_get_pipe_from_crtc_id {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]641 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]642 __u32 pipe;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]644};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]645#define I915_MADV_WILLNEED 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]646#define I915_MADV_DONTNEED 1
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]647#define __I915_MADV_PURGED 2
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]649struct drm_i915_gem_madvise {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]650 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]651 __u32 madv;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]652 __u32 retained;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]654};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]655#define I915_OVERLAY_TYPE_MASK 0xff
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]656#define I915_OVERLAY_YUV_PLANAR 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]657#define I915_OVERLAY_YUV_PACKED 0x02
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]659#define I915_OVERLAY_RGB 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]660#define I915_OVERLAY_DEPTH_MASK 0xff00
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]661#define I915_OVERLAY_RGB24 0x1000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]662#define I915_OVERLAY_RGB16 0x2000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]664#define I915_OVERLAY_RGB15 0x3000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]665#define I915_OVERLAY_YUV422 0x0100
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]666#define I915_OVERLAY_YUV411 0x0200
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]667#define I915_OVERLAY_YUV420 0x0300
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]669#define I915_OVERLAY_YUV410 0x0400
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]670#define I915_OVERLAY_SWAP_MASK 0xff0000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]671#define I915_OVERLAY_NO_SWAP 0x000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]672#define I915_OVERLAY_UV_SWAP 0x010000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]674#define I915_OVERLAY_Y_SWAP 0x020000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]675#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]676#define I915_OVERLAY_FLAGS_MASK 0xff000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]677#define I915_OVERLAY_ENABLE 0x01000000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]679struct drm_intel_overlay_put_image {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]680 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]681 __u32 bo_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]682 __u16 stride_Y;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]684 __u16 stride_UV;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]685 __u32 offset_Y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]686 __u32 offset_U;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]687 __u32 offset_V;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]689 __u16 src_width;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]690 __u16 src_height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]691 __u16 src_scan_width;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]692 __u16 src_scan_height;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]694 __u32 crtc_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]695 __u16 dst_x;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]696 __u16 dst_y;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]697 __u16 dst_width;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]699 __u16 dst_height;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]700};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]701#define I915_OVERLAY_UPDATE_ATTRS (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]702#define I915_OVERLAY_UPDATE_GAMMA (1 << 1)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]704#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]705struct drm_intel_overlay_attrs {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]706 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]707 __u32 color_key;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]709 __s32 brightness;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]710 __u32 contrast;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]711 __u32 saturation;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]712 __u32 gamma0;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]714 __u32 gamma1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]715 __u32 gamma2;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]716 __u32 gamma3;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]717 __u32 gamma4;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]719 __u32 gamma5;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]720};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]721#define I915_SET_COLORKEY_NONE (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]722#define I915_SET_COLORKEY_DESTINATION (1 << 1)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]724#define I915_SET_COLORKEY_SOURCE (1 << 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]725struct drm_intel_sprite_colorkey {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]726 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]727 __u32 min_value;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]729 __u32 channel_mask;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]730 __u32 max_value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]731 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]732};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]734struct drm_i915_gem_wait {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]735 __u32 bo_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]736 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]737 __s64 timeout_ns;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]739};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]740struct drm_i915_gem_context_create {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]741 __u32 ctx_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]742 __u32 pad;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]744};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]745struct drm_i915_gem_context_destroy {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]746 __u32 ctx_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]747 __u32 pad;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]749};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]750struct drm_i915_reg_read {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]751 __u64 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]752 __u64 val;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]754};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]755struct drm_i915_reset_stats {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]756 __u32 ctx_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]757 __u32 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]759 __u32 reset_count;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]760 __u32 batch_active;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]761 __u32 batch_pending;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]762 __u32 pad;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]764};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]765struct drm_i915_gem_userptr {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]766 __u64 user_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]767 __u64 user_size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]769 __u32 flags;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]770#define I915_USERPTR_READ_ONLY 0x1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]771#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]772 __u32 handle;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]774};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]775struct drm_i915_gem_context_param {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]776 __u32 ctx_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]777 __u32 size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]779 __u64 param;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]780#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]781#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
782#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]784#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]785 __u64 value;
786};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]787#ifdef __cplusplus
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]789#endif
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]790#endif