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gerrit.omnirom.org / android_bionic / 05d08e9716b5974d6ed08973f44930804890b902 / . / libc / kernel / uapi / drm / i915_drm.h
blob: da685762f3247d7098d31c7f28c0ab3bc31ab5ab [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_I915_DRM_H_
20#define _UAPI_I915_DRM_H_
21#include <drm/drm.h>
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]22#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]24#define I915_ERROR_UEVENT "ERROR"
25#define I915_RESET_UEVENT "RESET"
26#define I915_NR_TEX_REGIONS 255
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27#define I915_LOG_MIN_TEX_REGION_SIZE 14
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29typedef struct _drm_i915_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]30 enum {
31 I915_INIT_DMA = 0x01,
32 I915_CLEANUP_DMA = 0x02,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]34 I915_RESUME_DMA = 0x03
35 } func;
36 unsigned int mmio_offset;
37 int sarea_priv_offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39 unsigned int ring_start;
40 unsigned int ring_end;
41 unsigned int ring_size;
42 unsigned int front_offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44 unsigned int back_offset;
45 unsigned int depth_offset;
46 unsigned int w;
47 unsigned int h;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]49 unsigned int pitch;
50 unsigned int pitch_bits;
51 unsigned int back_pitch;
52 unsigned int depth_pitch;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54 unsigned int cpp;
55 unsigned int chipset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]56} drm_i915_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]57typedef struct _drm_i915_sarea {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
60 int last_upload;
61 int last_enqueue;
62 int last_dispatch;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]64 int ctxOwner;
65 int texAge;
66 int pf_enabled;
67 int pf_active;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]69 int pf_current_page;
70 int perf_boxes;
71 int width, height;
72 drm_handle_t front_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]74 int front_offset;
75 int front_size;
76 drm_handle_t back_handle;
77 int back_offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 int back_size;
80 drm_handle_t depth_handle;
81 int depth_offset;
82 int depth_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]84 drm_handle_t tex_handle;
85 int tex_offset;
86 int tex_size;
87 int log_tex_granularity;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]89 int pitch;
90 int rotation;
91 int rotated_offset;
92 int rotated_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]94 int rotated_pitch;
95 int virtualX, virtualY;
96 unsigned int front_tiled;
97 unsigned int back_tiled;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]99 unsigned int depth_tiled;
100 unsigned int rotated_tiled;
101 unsigned int rotated2_tiled;
102 int pipeA_x;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]104 int pipeA_y;
105 int pipeA_w;
106 int pipeA_h;
107 int pipeB_x;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]109 int pipeB_y;
110 int pipeB_w;
111 int pipeB_h;
112 drm_handle_t unused_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 __u32 unused1, unused2, unused3;
115 __u32 front_bo_handle;
116 __u32 back_bo_handle;
117 __u32 unused_bo_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 __u32 depth_bo_handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]120} drm_i915_sarea_t;
121#define planeA_x pipeA_x
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122#define planeA_y pipeA_y
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define planeA_w pipeA_w
125#define planeA_h pipeA_h
126#define planeB_x pipeB_x
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127#define planeB_y pipeB_y
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define planeB_w pipeB_w
130#define planeB_h pipeB_h
131#define I915_BOX_RING_EMPTY 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]132#define I915_BOX_FLIP 0x2
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define I915_BOX_WAIT 0x4
135#define I915_BOX_TEXTURE_LOAD 0x8
136#define I915_BOX_LOST_CONTEXT 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]137#define DRM_I915_INIT 0x00
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define DRM_I915_FLUSH 0x01
140#define DRM_I915_FLIP 0x02
141#define DRM_I915_BATCHBUFFER 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]142#define DRM_I915_IRQ_EMIT 0x04
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define DRM_I915_IRQ_WAIT 0x05
145#define DRM_I915_GETPARAM 0x06
146#define DRM_I915_SETPARAM 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]147#define DRM_I915_ALLOC 0x08
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define DRM_I915_FREE 0x09
150#define DRM_I915_INIT_HEAP 0x0a
151#define DRM_I915_CMDBUFFER 0x0b
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]152#define DRM_I915_DESTROY_HEAP 0x0c
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154#define DRM_I915_SET_VBLANK_PIPE 0x0d
155#define DRM_I915_GET_VBLANK_PIPE 0x0e
156#define DRM_I915_VBLANK_SWAP 0x0f
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]157#define DRM_I915_HWS_ADDR 0x11
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159#define DRM_I915_GEM_INIT 0x13
160#define DRM_I915_GEM_EXECBUFFER 0x14
161#define DRM_I915_GEM_PIN 0x15
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]162#define DRM_I915_GEM_UNPIN 0x16
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164#define DRM_I915_GEM_BUSY 0x17
165#define DRM_I915_GEM_THROTTLE 0x18
166#define DRM_I915_GEM_ENTERVT 0x19
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]167#define DRM_I915_GEM_LEAVEVT 0x1a
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169#define DRM_I915_GEM_CREATE 0x1b
170#define DRM_I915_GEM_PREAD 0x1c
171#define DRM_I915_GEM_PWRITE 0x1d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172#define DRM_I915_GEM_MMAP 0x1e
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174#define DRM_I915_GEM_SET_DOMAIN 0x1f
175#define DRM_I915_GEM_SW_FINISH 0x20
176#define DRM_I915_GEM_SET_TILING 0x21
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]177#define DRM_I915_GEM_GET_TILING 0x22
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define DRM_I915_GEM_GET_APERTURE 0x23
180#define DRM_I915_GEM_MMAP_GTT 0x24
181#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182#define DRM_I915_GEM_MADVISE 0x26
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
185#define DRM_I915_OVERLAY_ATTRS 0x28
186#define DRM_I915_GEM_EXECBUFFER2 0x29
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]187#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
190#define DRM_I915_GEM_WAIT 0x2c
191#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]192#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define DRM_I915_GEM_SET_CACHING 0x2f
195#define DRM_I915_GEM_GET_CACHING 0x30
196#define DRM_I915_REG_READ 0x31
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]197#define DRM_I915_GET_RESET_STATS 0x32
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]199#define DRM_I915_GEM_USERPTR 0x33
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]200#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
201#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]202#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]204#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH)
205#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]206#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]207#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]209#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]210#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]211#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]214#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
215#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]216#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
217#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]219#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
220#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]221#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
225#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]226#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
230#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]231#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]232#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]234#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]235#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]236#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]237#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]239#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
240#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]241#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]242#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]244#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
245#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]246#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
247#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]249#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]250#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]251#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]252#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
255#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]256#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]257#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]259#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
260#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]261#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
262#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]264#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]265#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
266#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267typedef struct drm_i915_batchbuffer {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]269 int start;
270 int used;
271 int DR1;
272 int DR4;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]274 int num_cliprects;
275 struct drm_clip_rect __user * cliprects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]276} drm_i915_batchbuffer_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]277typedef struct _drm_i915_cmdbuffer {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]279 char __user * buf;
280 int sz;
281 int DR1;
282 int DR4;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]284 int num_cliprects;
285 struct drm_clip_rect __user * cliprects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]286} drm_i915_cmdbuffer_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]287typedef struct drm_i915_irq_emit {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]289 int __user * irq_seq;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]290} drm_i915_irq_emit_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]291typedef struct drm_i915_irq_wait {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]292 int irq_seq;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]294} drm_i915_irq_wait_t;
295#define I915_PARAM_IRQ_ACTIVE 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]296#define I915_PARAM_ALLOW_BATCHBUFFER 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]297#define I915_PARAM_LAST_DISPATCH 3
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299#define I915_PARAM_CHIPSET_ID 4
300#define I915_PARAM_HAS_GEM 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]301#define I915_PARAM_NUM_FENCES_AVAIL 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302#define I915_PARAM_HAS_OVERLAY 7
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304#define I915_PARAM_HAS_PAGEFLIPPING 8
305#define I915_PARAM_HAS_EXECBUF2 9
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]306#define I915_PARAM_HAS_BSD 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]307#define I915_PARAM_HAS_BLT 11
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]309#define I915_PARAM_HAS_RELAXED_FENCING 12
310#define I915_PARAM_HAS_COHERENT_RINGS 13
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]311#define I915_PARAM_HAS_EXEC_CONSTANTS 14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]312#define I915_PARAM_HAS_RELAXED_DELTA 15
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]314#define I915_PARAM_HAS_GEN7_SOL_RESET 16
315#define I915_PARAM_HAS_LLC 17
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]316#define I915_PARAM_HAS_ALIASING_PPGTT 18
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]317#define I915_PARAM_HAS_WAIT_TIMEOUT 19
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319#define I915_PARAM_HAS_SEMAPHORES 20
320#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]321#define I915_PARAM_HAS_VEBOX 22
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]322#define I915_PARAM_HAS_SECURE_BATCHES 23
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]324#define I915_PARAM_HAS_PINNED_BATCHES 24
325#define I915_PARAM_HAS_EXEC_NO_RELOC 25
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]326#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
327#define I915_PARAM_HAS_WT 27
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
329#define I915_PARAM_CMD_PARSER_VERSION 28
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]330#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
331#define I915_PARAM_MMAP_VERSION 30
332#define I915_PARAM_HAS_BSD2 31
333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
334#define I915_PARAM_REVISION 32
335#define I915_PARAM_SUBSLICE_TOTAL 33
336#define I915_PARAM_EU_TOTAL 34
337#define I915_PARAM_HAS_GPU_RESET 35
338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
339#define I915_PARAM_HAS_RESOURCE_STREAMER 36
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]340typedef struct drm_i915_getparam {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]341 __s32 param;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]342 int __user * value;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]344} drm_i915_getparam_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]345#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
346#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
347#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]349#define I915_SETPARAM_NUM_USED_FENCES 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]350typedef struct drm_i915_setparam {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]351 int param;
352 int value;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]354} drm_i915_setparam_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]355#define I915_MEM_REGION_AGP 1
356typedef struct drm_i915_mem_alloc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]357 int region;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]359 int alignment;
360 int size;
361 int __user * region_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]362} drm_i915_mem_alloc_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]364typedef struct drm_i915_mem_free {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]365 int region;
366 int region_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]367} drm_i915_mem_free_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]369typedef struct drm_i915_mem_init_heap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]370 int region;
371 int size;
372 int start;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374} drm_i915_mem_init_heap_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]375typedef struct drm_i915_mem_destroy_heap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]376 int region;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]377} drm_i915_mem_destroy_heap_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]379#define DRM_I915_VBLANK_PIPE_A 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]380#define DRM_I915_VBLANK_PIPE_B 2
381typedef struct drm_i915_vblank_pipe {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]382 int pipe;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]384} drm_i915_vblank_pipe_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]385typedef struct drm_i915_vblank_swap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]386 drm_drawable_t drawable;
387 enum drm_vblank_seq_type seqtype;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]389 unsigned int sequence;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]390} drm_i915_vblank_swap_t;
391typedef struct drm_i915_hws_addr {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]392 __u64 addr;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]394} drm_i915_hws_addr_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]395struct drm_i915_gem_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]396 __u64 gtt_start;
397 __u64 gtt_end;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]399};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]400struct drm_i915_gem_create {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]401 __u64 size;
402 __u32 handle;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]404 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]405};
406struct drm_i915_gem_pread {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]407 __u32 handle;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]409 __u32 pad;
410 __u64 offset;
411 __u64 size;
412 __u64 data_ptr;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]414};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]415struct drm_i915_gem_pwrite {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]416 __u32 handle;
417 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]419 __u64 offset;
420 __u64 size;
421 __u64 data_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]422};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]424struct drm_i915_gem_mmap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]425 __u32 handle;
426 __u32 pad;
427 __u64 offset;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]429 __u64 size;
430 __u64 addr_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]431 __u64 flags;
432#define I915_MMAP_WC 0x1
433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]434};
435struct drm_i915_gem_mmap_gtt {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]436 __u32 handle;
437 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]439 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]440};
441struct drm_i915_gem_set_domain {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]442 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]444 __u32 read_domains;
445 __u32 write_domain;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]446};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]447struct drm_i915_gem_sw_finish {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]449 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]450};
451struct drm_i915_gem_relocation_entry {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]452 __u32 target_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]454 __u32 delta;
455 __u64 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]456 __u64 presumed_offset;
457 __u32 read_domains;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]459 __u32 write_domain;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]460};
461#define I915_GEM_DOMAIN_CPU 0x00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]462#define I915_GEM_DOMAIN_RENDER 0x00000002
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]464#define I915_GEM_DOMAIN_SAMPLER 0x00000004
465#define I915_GEM_DOMAIN_COMMAND 0x00000008
466#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]467#define I915_GEM_DOMAIN_VERTEX 0x00000020
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]469#define I915_GEM_DOMAIN_GTT 0x00000040
470struct drm_i915_gem_exec_object {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]471 __u32 handle;
472 __u32 relocation_count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]474 __u64 relocs_ptr;
475 __u64 alignment;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]476 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]477};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]479struct drm_i915_gem_execbuffer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]480 __u64 buffers_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]481 __u32 buffer_count;
482 __u32 batch_start_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]484 __u32 batch_len;
485 __u32 DR1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]486 __u32 DR4;
487 __u32 num_cliprects;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]489 __u64 cliprects_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]490};
491struct drm_i915_gem_exec_object2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]492 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]494 __u32 relocation_count;
495 __u64 relocs_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]496 __u64 alignment;
497 __u64 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]499#define EXEC_OBJECT_NEEDS_FENCE (1 << 0)
500#define EXEC_OBJECT_NEEDS_GTT (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]501#define EXEC_OBJECT_WRITE (1 << 2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]502#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3)
503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
504#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_SUPPORTS_48B_ADDRESS << 1)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]505 __u64 flags;
506 __u64 rsvd1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]507 __u64 rsvd2;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]509};
510struct drm_i915_gem_execbuffer2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]511 __u64 buffers_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]512 __u32 buffer_count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]514 __u32 batch_start_offset;
515 __u32 batch_len;
516 __u32 DR1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]517 __u32 DR4;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]519 __u32 num_cliprects;
520 __u64 cliprects_ptr;
521#define I915_EXEC_RING_MASK (7 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]522#define I915_EXEC_DEFAULT (0 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]524#define I915_EXEC_RENDER (1 << 0)
525#define I915_EXEC_BSD (2 << 0)
526#define I915_EXEC_BLT (3 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]527#define I915_EXEC_VEBOX (4 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]529#define I915_EXEC_CONSTANTS_MASK (3 << 6)
530#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6)
531#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]532#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]534 __u64 flags;
535 __u64 rsvd1;
536 __u64 rsvd2;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]537};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]539#define I915_EXEC_GEN7_SOL_RESET (1 << 8)
540#define I915_EXEC_SECURE (1 << 9)
541#define I915_EXEC_IS_PINNED (1 << 10)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]542#define I915_EXEC_NO_RELOC (1 << 11)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]544#define I915_EXEC_HANDLE_LUT (1 << 12)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]545#define I915_EXEC_BSD_MASK (3 << 13)
546#define I915_EXEC_BSD_DEFAULT (0 << 13)
547#define I915_EXEC_BSD_RING1 (1 << 13)
548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
549#define I915_EXEC_BSD_RING2 (2 << 13)
550#define I915_EXEC_RESOURCE_STREAMER (1 << 15)
551#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_RESOURCE_STREAMER << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]552#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]554#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
555#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]556struct drm_i915_gem_pin {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]557 __u32 handle;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]559 __u32 pad;
560 __u64 alignment;
561 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]562};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]564struct drm_i915_gem_unpin {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]565 __u32 handle;
566 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]567};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]569struct drm_i915_gem_busy {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]570 __u32 handle;
571 __u32 busy;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]572};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]574#define I915_CACHING_NONE 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]575#define I915_CACHING_CACHED 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]576#define I915_CACHING_DISPLAY 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]577struct drm_i915_gem_caching {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]579 __u32 handle;
580 __u32 caching;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]581};
582#define I915_TILING_NONE 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]584#define I915_TILING_X 1
585#define I915_TILING_Y 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]586#define I915_BIT_6_SWIZZLE_NONE 0
587#define I915_BIT_6_SWIZZLE_9 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]589#define I915_BIT_6_SWIZZLE_9_10 2
590#define I915_BIT_6_SWIZZLE_9_11 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]591#define I915_BIT_6_SWIZZLE_9_10_11 4
592#define I915_BIT_6_SWIZZLE_UNKNOWN 5
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]594#define I915_BIT_6_SWIZZLE_9_17 6
595#define I915_BIT_6_SWIZZLE_9_10_17 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]596struct drm_i915_gem_set_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]597 __u32 handle;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]599 __u32 tiling_mode;
600 __u32 stride;
601 __u32 swizzle_mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]602};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]604struct drm_i915_gem_get_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]605 __u32 handle;
606 __u32 tiling_mode;
607 __u32 swizzle_mode;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]609 __u32 phys_swizzle_mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]610};
611struct drm_i915_gem_get_aperture {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]612 __u64 aper_size;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]614 __u64 aper_available_size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]615};
616struct drm_i915_get_pipe_from_crtc_id {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]617 __u32 crtc_id;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]619 __u32 pipe;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]620};
621#define I915_MADV_WILLNEED 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]622#define I915_MADV_DONTNEED 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]624#define __I915_MADV_PURGED 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]625struct drm_i915_gem_madvise {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]626 __u32 handle;
627 __u32 madv;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]629 __u32 retained;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]630};
631#define I915_OVERLAY_TYPE_MASK 0xff
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]632#define I915_OVERLAY_YUV_PLANAR 0x01
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]634#define I915_OVERLAY_YUV_PACKED 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]635#define I915_OVERLAY_RGB 0x03
636#define I915_OVERLAY_DEPTH_MASK 0xff00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]637#define I915_OVERLAY_RGB24 0x1000
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]639#define I915_OVERLAY_RGB16 0x2000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]640#define I915_OVERLAY_RGB15 0x3000
641#define I915_OVERLAY_YUV422 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]642#define I915_OVERLAY_YUV411 0x0200
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]644#define I915_OVERLAY_YUV420 0x0300
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]645#define I915_OVERLAY_YUV410 0x0400
646#define I915_OVERLAY_SWAP_MASK 0xff0000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]647#define I915_OVERLAY_NO_SWAP 0x000000
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]649#define I915_OVERLAY_UV_SWAP 0x010000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]650#define I915_OVERLAY_Y_SWAP 0x020000
651#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]652#define I915_OVERLAY_FLAGS_MASK 0xff000000
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]654#define I915_OVERLAY_ENABLE 0x01000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]655struct drm_intel_overlay_put_image {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]656 __u32 flags;
657 __u32 bo_handle;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]659 __u16 stride_Y;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]660 __u16 stride_UV;
661 __u32 offset_Y;
662 __u32 offset_U;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]664 __u32 offset_V;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]665 __u16 src_width;
666 __u16 src_height;
667 __u16 src_scan_width;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]669 __u16 src_scan_height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]670 __u32 crtc_id;
671 __u16 dst_x;
672 __u16 dst_y;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]674 __u16 dst_width;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]675 __u16 dst_height;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]676};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]677#define I915_OVERLAY_UPDATE_ATTRS (1 << 0)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]679#define I915_OVERLAY_UPDATE_GAMMA (1 << 1)
680#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]681struct drm_intel_overlay_attrs {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]682 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]684 __u32 color_key;
685 __s32 brightness;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]686 __u32 contrast;
687 __u32 saturation;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]689 __u32 gamma0;
690 __u32 gamma1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]691 __u32 gamma2;
692 __u32 gamma3;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]694 __u32 gamma4;
695 __u32 gamma5;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]696};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]697#define I915_SET_COLORKEY_NONE (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]699#define I915_SET_COLORKEY_DESTINATION (1 << 1)
700#define I915_SET_COLORKEY_SOURCE (1 << 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]701struct drm_intel_sprite_colorkey {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]702 __u32 plane_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]704 __u32 min_value;
705 __u32 channel_mask;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]706 __u32 max_value;
707 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]709};
710struct drm_i915_gem_wait {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]711 __u32 bo_handle;
712 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]714 __s64 timeout_ns;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]715};
716struct drm_i915_gem_context_create {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]717 __u32 ctx_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]719 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]720};
721struct drm_i915_gem_context_destroy {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]722 __u32 ctx_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]724 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]725};
726struct drm_i915_reg_read {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]727 __u64 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]729 __u64 val;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]730};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]731struct drm_i915_reset_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]732 __u32 ctx_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]734 __u32 flags;
735 __u32 reset_count;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]736 __u32 batch_active;
737 __u32 batch_pending;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]739 __u32 pad;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]740};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]741struct drm_i915_gem_userptr {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]742 __u64 user_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]744 __u64 user_size;
745 __u32 flags;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]746#define I915_USERPTR_READ_ONLY 0x1
747#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]749 __u32 handle;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]750};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]751struct drm_i915_gem_context_param {
752 __u32 ctx_id;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]754 __u32 size;
755 __u64 param;
756#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
757#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
759 __u64 value;
760};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]761#endif