blob: 64e2cae9f6d652b7155ecd27cf227b74c4f5cfd0 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef _DVBFRONTEND_H_
8#define _DVBFRONTEND_H_
9#include <linux/types.h>
Christopher Ferris05d08e92016-02-04 13:16:38 -080010enum fe_caps {
Tao Baod7db5942015-01-28 10:07:51 -080011 FE_IS_STUPID = 0,
12 FE_CAN_INVERSION_AUTO = 0x1,
Tao Baod7db5942015-01-28 10:07:51 -080013 FE_CAN_FEC_1_2 = 0x2,
14 FE_CAN_FEC_2_3 = 0x4,
15 FE_CAN_FEC_3_4 = 0x8,
16 FE_CAN_FEC_4_5 = 0x10,
Tao Baod7db5942015-01-28 10:07:51 -080017 FE_CAN_FEC_5_6 = 0x20,
18 FE_CAN_FEC_6_7 = 0x40,
19 FE_CAN_FEC_7_8 = 0x80,
20 FE_CAN_FEC_8_9 = 0x100,
Tao Baod7db5942015-01-28 10:07:51 -080021 FE_CAN_FEC_AUTO = 0x200,
22 FE_CAN_QPSK = 0x400,
23 FE_CAN_QAM_16 = 0x800,
24 FE_CAN_QAM_32 = 0x1000,
Tao Baod7db5942015-01-28 10:07:51 -080025 FE_CAN_QAM_64 = 0x2000,
26 FE_CAN_QAM_128 = 0x4000,
27 FE_CAN_QAM_256 = 0x8000,
28 FE_CAN_QAM_AUTO = 0x10000,
Tao Baod7db5942015-01-28 10:07:51 -080029 FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000,
30 FE_CAN_BANDWIDTH_AUTO = 0x40000,
31 FE_CAN_GUARD_INTERVAL_AUTO = 0x80000,
32 FE_CAN_HIERARCHY_AUTO = 0x100000,
Tao Baod7db5942015-01-28 10:07:51 -080033 FE_CAN_8VSB = 0x200000,
34 FE_CAN_16VSB = 0x400000,
35 FE_HAS_EXTENDED_CAPS = 0x800000,
36 FE_CAN_MULTISTREAM = 0x4000000,
Tao Baod7db5942015-01-28 10:07:51 -080037 FE_CAN_TURBO_FEC = 0x8000000,
38 FE_CAN_2G_MODULATION = 0x10000000,
39 FE_NEEDS_BENDING = 0x20000000,
40 FE_CAN_RECOVER = 0x40000000,
Tao Baod7db5942015-01-28 10:07:51 -080041 FE_CAN_MUTE_TS = 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080042};
Christopher Ferris1308ad32017-11-14 17:32:13 -080043enum fe_type {
44 FE_QPSK,
45 FE_QAM,
46 FE_OFDM,
47 FE_ATSC
48};
Ben Cheng655a7c02013-10-16 16:09:24 -070049struct dvb_frontend_info {
Tao Baod7db5942015-01-28 10:07:51 -080050 char name[128];
Christopher Ferris05d08e92016-02-04 13:16:38 -080051 enum fe_type type;
Tao Baod7db5942015-01-28 10:07:51 -080052 __u32 frequency_min;
53 __u32 frequency_max;
54 __u32 frequency_stepsize;
Tao Baod7db5942015-01-28 10:07:51 -080055 __u32 frequency_tolerance;
56 __u32 symbol_rate_min;
57 __u32 symbol_rate_max;
58 __u32 symbol_rate_tolerance;
Tao Baod7db5942015-01-28 10:07:51 -080059 __u32 notifier_delay;
Christopher Ferris05d08e92016-02-04 13:16:38 -080060 enum fe_caps caps;
Ben Cheng655a7c02013-10-16 16:09:24 -070061};
62struct dvb_diseqc_master_cmd {
Tao Baod7db5942015-01-28 10:07:51 -080063 __u8 msg[6];
64 __u8 msg_len;
Ben Cheng655a7c02013-10-16 16:09:24 -070065};
66struct dvb_diseqc_slave_reply {
Tao Baod7db5942015-01-28 10:07:51 -080067 __u8 msg[4];
68 __u8 msg_len;
69 int timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -070070};
Christopher Ferris05d08e92016-02-04 13:16:38 -080071enum fe_sec_voltage {
Tao Baod7db5942015-01-28 10:07:51 -080072 SEC_VOLTAGE_13,
73 SEC_VOLTAGE_18,
74 SEC_VOLTAGE_OFF
Christopher Ferris05d08e92016-02-04 13:16:38 -080075};
76enum fe_sec_tone_mode {
Tao Baod7db5942015-01-28 10:07:51 -080077 SEC_TONE_ON,
78 SEC_TONE_OFF
Christopher Ferris05d08e92016-02-04 13:16:38 -080079};
80enum fe_sec_mini_cmd {
Tao Baod7db5942015-01-28 10:07:51 -080081 SEC_MINI_A,
82 SEC_MINI_B
Christopher Ferris05d08e92016-02-04 13:16:38 -080083};
84enum fe_status {
Christopher Ferris1308ad32017-11-14 17:32:13 -080085 FE_NONE = 0x00,
Tao Baod7db5942015-01-28 10:07:51 -080086 FE_HAS_SIGNAL = 0x01,
87 FE_HAS_CARRIER = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -080088 FE_HAS_VITERBI = 0x04,
89 FE_HAS_SYNC = 0x08,
90 FE_HAS_LOCK = 0x10,
91 FE_TIMEDOUT = 0x20,
Tao Baod7db5942015-01-28 10:07:51 -080092 FE_REINIT = 0x40,
Christopher Ferris05d08e92016-02-04 13:16:38 -080093};
94enum fe_spectral_inversion {
Tao Baod7db5942015-01-28 10:07:51 -080095 INVERSION_OFF,
Tao Baod7db5942015-01-28 10:07:51 -080096 INVERSION_ON,
97 INVERSION_AUTO
Christopher Ferris05d08e92016-02-04 13:16:38 -080098};
99enum fe_code_rate {
Tao Baod7db5942015-01-28 10:07:51 -0800100 FEC_NONE = 0,
101 FEC_1_2,
102 FEC_2_3,
103 FEC_3_4,
Tao Baod7db5942015-01-28 10:07:51 -0800104 FEC_4_5,
105 FEC_5_6,
106 FEC_6_7,
107 FEC_7_8,
Tao Baod7db5942015-01-28 10:07:51 -0800108 FEC_8_9,
109 FEC_AUTO,
110 FEC_3_5,
111 FEC_9_10,
Tao Baod7db5942015-01-28 10:07:51 -0800112 FEC_2_5,
Christopher Ferris8b7fdc92023-02-21 13:36:32 -0800113 FEC_1_3,
114 FEC_1_4,
115 FEC_5_9,
116 FEC_7_9,
117 FEC_8_15,
118 FEC_11_15,
119 FEC_13_18,
120 FEC_9_20,
121 FEC_11_20,
122 FEC_23_36,
123 FEC_25_36,
124 FEC_13_45,
125 FEC_26_45,
126 FEC_28_45,
127 FEC_32_45,
128 FEC_77_90,
Christopher Ferris8666d042023-09-06 14:55:31 -0700129 FEC_11_45,
130 FEC_4_15,
131 FEC_14_45,
132 FEC_7_15,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800133};
134enum fe_modulation {
Tao Baod7db5942015-01-28 10:07:51 -0800135 QPSK,
Tao Baod7db5942015-01-28 10:07:51 -0800136 QAM_16,
137 QAM_32,
138 QAM_64,
139 QAM_128,
Tao Baod7db5942015-01-28 10:07:51 -0800140 QAM_256,
141 QAM_AUTO,
142 VSB_8,
143 VSB_16,
Tao Baod7db5942015-01-28 10:07:51 -0800144 PSK_8,
145 APSK_16,
146 APSK_32,
147 DQPSK,
Tao Baod7db5942015-01-28 10:07:51 -0800148 QAM_4_NR,
Christopher Ferris8b7fdc92023-02-21 13:36:32 -0800149 QAM_1024,
150 QAM_4096,
151 APSK_8_L,
152 APSK_16_L,
153 APSK_32_L,
154 APSK_64,
155 APSK_64_L,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800156};
157enum fe_transmit_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800158 TRANSMISSION_MODE_2K,
Tao Baod7db5942015-01-28 10:07:51 -0800159 TRANSMISSION_MODE_8K,
160 TRANSMISSION_MODE_AUTO,
161 TRANSMISSION_MODE_4K,
162 TRANSMISSION_MODE_1K,
Tao Baod7db5942015-01-28 10:07:51 -0800163 TRANSMISSION_MODE_16K,
164 TRANSMISSION_MODE_32K,
165 TRANSMISSION_MODE_C1,
166 TRANSMISSION_MODE_C3780,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800167};
168enum fe_guard_interval {
Tao Baod7db5942015-01-28 10:07:51 -0800169 GUARD_INTERVAL_1_32,
Tao Baod7db5942015-01-28 10:07:51 -0800170 GUARD_INTERVAL_1_16,
171 GUARD_INTERVAL_1_8,
172 GUARD_INTERVAL_1_4,
173 GUARD_INTERVAL_AUTO,
Tao Baod7db5942015-01-28 10:07:51 -0800174 GUARD_INTERVAL_1_128,
175 GUARD_INTERVAL_19_128,
176 GUARD_INTERVAL_19_256,
177 GUARD_INTERVAL_PN420,
Tao Baod7db5942015-01-28 10:07:51 -0800178 GUARD_INTERVAL_PN595,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800179 GUARD_INTERVAL_PN945,
Christopher Ferris8b7fdc92023-02-21 13:36:32 -0800180 GUARD_INTERVAL_1_64,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800181};
182enum fe_hierarchy {
Tao Baod7db5942015-01-28 10:07:51 -0800183 HIERARCHY_NONE,
184 HIERARCHY_1,
185 HIERARCHY_2,
186 HIERARCHY_4,
Tao Baod7db5942015-01-28 10:07:51 -0800187 HIERARCHY_AUTO
Christopher Ferris05d08e92016-02-04 13:16:38 -0800188};
Ben Cheng655a7c02013-10-16 16:09:24 -0700189enum fe_interleaving {
Tao Baod7db5942015-01-28 10:07:51 -0800190 INTERLEAVING_NONE,
Tao Baod7db5942015-01-28 10:07:51 -0800191 INTERLEAVING_AUTO,
192 INTERLEAVING_240,
193 INTERLEAVING_720,
Ben Cheng655a7c02013-10-16 16:09:24 -0700194};
Ben Cheng655a7c02013-10-16 16:09:24 -0700195#define DTV_UNDEFINED 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700196#define DTV_TUNE 1
197#define DTV_CLEAR 2
198#define DTV_FREQUENCY 3
199#define DTV_MODULATION 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700200#define DTV_BANDWIDTH_HZ 5
201#define DTV_INVERSION 6
202#define DTV_DISEQC_MASTER 7
203#define DTV_SYMBOL_RATE 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700204#define DTV_INNER_FEC 9
205#define DTV_VOLTAGE 10
206#define DTV_TONE 11
207#define DTV_PILOT 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700208#define DTV_ROLLOFF 13
209#define DTV_DISEQC_SLAVE_REPLY 14
210#define DTV_FE_CAPABILITY_COUNT 15
211#define DTV_FE_CAPABILITY 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700212#define DTV_DELIVERY_SYSTEM 17
213#define DTV_ISDBT_PARTIAL_RECEPTION 18
214#define DTV_ISDBT_SOUND_BROADCASTING 19
215#define DTV_ISDBT_SB_SUBCHANNEL_ID 20
Ben Cheng655a7c02013-10-16 16:09:24 -0700216#define DTV_ISDBT_SB_SEGMENT_IDX 21
217#define DTV_ISDBT_SB_SEGMENT_COUNT 22
218#define DTV_ISDBT_LAYERA_FEC 23
219#define DTV_ISDBT_LAYERA_MODULATION 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700220#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25
221#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26
222#define DTV_ISDBT_LAYERB_FEC 27
223#define DTV_ISDBT_LAYERB_MODULATION 28
Ben Cheng655a7c02013-10-16 16:09:24 -0700224#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29
225#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30
226#define DTV_ISDBT_LAYERC_FEC 31
227#define DTV_ISDBT_LAYERC_MODULATION 32
Ben Cheng655a7c02013-10-16 16:09:24 -0700228#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33
229#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34
230#define DTV_API_VERSION 35
231#define DTV_CODE_RATE_HP 36
Ben Cheng655a7c02013-10-16 16:09:24 -0700232#define DTV_CODE_RATE_LP 37
233#define DTV_GUARD_INTERVAL 38
234#define DTV_TRANSMISSION_MODE 39
235#define DTV_HIERARCHY 40
Ben Cheng655a7c02013-10-16 16:09:24 -0700236#define DTV_ISDBT_LAYER_ENABLED 41
237#define DTV_STREAM_ID 42
238#define DTV_ISDBS_TS_ID_LEGACY DTV_STREAM_ID
239#define DTV_DVBT2_PLP_ID_LEGACY 43
Ben Cheng655a7c02013-10-16 16:09:24 -0700240#define DTV_ENUM_DELSYS 44
241#define DTV_ATSCMH_FIC_VER 45
242#define DTV_ATSCMH_PARADE_ID 46
243#define DTV_ATSCMH_NOG 47
Ben Cheng655a7c02013-10-16 16:09:24 -0700244#define DTV_ATSCMH_TNOG 48
245#define DTV_ATSCMH_SGN 49
246#define DTV_ATSCMH_PRC 50
247#define DTV_ATSCMH_RS_FRAME_MODE 51
Ben Cheng655a7c02013-10-16 16:09:24 -0700248#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52
249#define DTV_ATSCMH_RS_CODE_MODE_PRI 53
250#define DTV_ATSCMH_RS_CODE_MODE_SEC 54
251#define DTV_ATSCMH_SCCC_BLOCK_MODE 55
Ben Cheng655a7c02013-10-16 16:09:24 -0700252#define DTV_ATSCMH_SCCC_CODE_MODE_A 56
253#define DTV_ATSCMH_SCCC_CODE_MODE_B 57
254#define DTV_ATSCMH_SCCC_CODE_MODE_C 58
255#define DTV_ATSCMH_SCCC_CODE_MODE_D 59
Ben Cheng655a7c02013-10-16 16:09:24 -0700256#define DTV_INTERLEAVING 60
257#define DTV_LNA 61
258#define DTV_STAT_SIGNAL_STRENGTH 62
259#define DTV_STAT_CNR 63
Ben Cheng655a7c02013-10-16 16:09:24 -0700260#define DTV_STAT_PRE_ERROR_BIT_COUNT 64
261#define DTV_STAT_PRE_TOTAL_BIT_COUNT 65
262#define DTV_STAT_POST_ERROR_BIT_COUNT 66
263#define DTV_STAT_POST_TOTAL_BIT_COUNT 67
Ben Cheng655a7c02013-10-16 16:09:24 -0700264#define DTV_STAT_ERROR_BLOCK_COUNT 68
265#define DTV_STAT_TOTAL_BLOCK_COUNT 69
Christopher Ferris76a1d452018-06-27 14:12:29 -0700266#define DTV_SCRAMBLING_SEQUENCE_INDEX 70
267#define DTV_MAX_COMMAND DTV_SCRAMBLING_SEQUENCE_INDEX
Christopher Ferris05d08e92016-02-04 13:16:38 -0800268enum fe_pilot {
Tao Baod7db5942015-01-28 10:07:51 -0800269 PILOT_ON,
270 PILOT_OFF,
271 PILOT_AUTO,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800272};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800273enum fe_rolloff {
Tao Baod7db5942015-01-28 10:07:51 -0800274 ROLLOFF_35,
275 ROLLOFF_20,
276 ROLLOFF_25,
Tao Baod7db5942015-01-28 10:07:51 -0800277 ROLLOFF_AUTO,
Christopher Ferris8b7fdc92023-02-21 13:36:32 -0800278 ROLLOFF_15,
279 ROLLOFF_10,
280 ROLLOFF_5,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800281};
282enum fe_delivery_system {
Tao Baod7db5942015-01-28 10:07:51 -0800283 SYS_UNDEFINED,
Tao Baod7db5942015-01-28 10:07:51 -0800284 SYS_DVBC_ANNEX_A,
285 SYS_DVBC_ANNEX_B,
286 SYS_DVBT,
287 SYS_DSS,
Tao Baod7db5942015-01-28 10:07:51 -0800288 SYS_DVBS,
289 SYS_DVBS2,
290 SYS_DVBH,
291 SYS_ISDBT,
Tao Baod7db5942015-01-28 10:07:51 -0800292 SYS_ISDBS,
293 SYS_ISDBC,
294 SYS_ATSC,
295 SYS_ATSCMH,
Tao Baod7db5942015-01-28 10:07:51 -0800296 SYS_DTMB,
297 SYS_CMMB,
298 SYS_DAB,
299 SYS_DVBT2,
Tao Baod7db5942015-01-28 10:07:51 -0800300 SYS_TURBO,
301 SYS_DVBC_ANNEX_C,
Christopher Ferris8b7fdc92023-02-21 13:36:32 -0800302 SYS_DVBC2,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800303};
Ben Cheng655a7c02013-10-16 16:09:24 -0700304#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A
Ben Cheng655a7c02013-10-16 16:09:24 -0700305#define SYS_DMBTH SYS_DTMB
306enum atscmh_sccc_block_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800307 ATSCMH_SCCC_BLK_SEP = 0,
308 ATSCMH_SCCC_BLK_COMB = 1,
Tao Baod7db5942015-01-28 10:07:51 -0800309 ATSCMH_SCCC_BLK_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700310};
311enum atscmh_sccc_code_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800312 ATSCMH_SCCC_CODE_HLF = 0,
Tao Baod7db5942015-01-28 10:07:51 -0800313 ATSCMH_SCCC_CODE_QTR = 1,
314 ATSCMH_SCCC_CODE_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700315};
316enum atscmh_rs_frame_ensemble {
Tao Baod7db5942015-01-28 10:07:51 -0800317 ATSCMH_RSFRAME_ENS_PRI = 0,
318 ATSCMH_RSFRAME_ENS_SEC = 1,
Ben Cheng655a7c02013-10-16 16:09:24 -0700319};
320enum atscmh_rs_frame_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800321 ATSCMH_RSFRAME_PRI_ONLY = 0,
322 ATSCMH_RSFRAME_PRI_SEC = 1,
323 ATSCMH_RSFRAME_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700324};
Ben Cheng655a7c02013-10-16 16:09:24 -0700325enum atscmh_rs_code_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800326 ATSCMH_RSCODE_211_187 = 0,
327 ATSCMH_RSCODE_223_187 = 1,
328 ATSCMH_RSCODE_235_187 = 2,
Tao Baod7db5942015-01-28 10:07:51 -0800329 ATSCMH_RSCODE_RES = 3,
Ben Cheng655a7c02013-10-16 16:09:24 -0700330};
331#define NO_STREAM_ID_FILTER (~0U)
332#define LNA_AUTO (~0U)
Ben Cheng655a7c02013-10-16 16:09:24 -0700333enum fecap_scale_params {
Tao Baod7db5942015-01-28 10:07:51 -0800334 FE_SCALE_NOT_AVAILABLE = 0,
335 FE_SCALE_DECIBEL,
336 FE_SCALE_RELATIVE,
337 FE_SCALE_COUNTER
Ben Cheng655a7c02013-10-16 16:09:24 -0700338};
339struct dtv_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800340 __u8 scale;
341 union {
Tao Baod7db5942015-01-28 10:07:51 -0800342 __u64 uvalue;
343 __s64 svalue;
344 };
345} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700346#define MAX_DTV_STATS 4
347struct dtv_fe_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800348 __u8 len;
349 struct dtv_stats stat[MAX_DTV_STATS];
Tao Baod7db5942015-01-28 10:07:51 -0800350} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700351struct dtv_property {
Tao Baod7db5942015-01-28 10:07:51 -0800352 __u32 cmd;
353 __u32 reserved[3];
Tao Baod7db5942015-01-28 10:07:51 -0800354 union {
355 __u32 data;
356 struct dtv_fe_stats st;
357 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800358 __u8 data[32];
359 __u32 len;
360 __u32 reserved1[3];
361 void * reserved2;
Tao Baod7db5942015-01-28 10:07:51 -0800362 } buffer;
363 } u;
364 int result;
365} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700366#define DTV_IOCTL_MAX_MSGS 64
367struct dtv_properties {
Tao Baod7db5942015-01-28 10:07:51 -0800368 __u32 num;
369 struct dtv_property * props;
Ben Cheng655a7c02013-10-16 16:09:24 -0700370};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800371#define FE_TUNE_MODE_ONESHOT 0x01
372#define FE_GET_INFO _IOR('o', 61, struct dvb_frontend_info)
373#define FE_DISEQC_RESET_OVERLOAD _IO('o', 62)
374#define FE_DISEQC_SEND_MASTER_CMD _IOW('o', 63, struct dvb_diseqc_master_cmd)
375#define FE_DISEQC_RECV_SLAVE_REPLY _IOR('o', 64, struct dvb_diseqc_slave_reply)
376#define FE_DISEQC_SEND_BURST _IO('o', 65)
377#define FE_SET_TONE _IO('o', 66)
378#define FE_SET_VOLTAGE _IO('o', 67)
379#define FE_ENABLE_HIGH_LNB_VOLTAGE _IO('o', 68)
380#define FE_READ_STATUS _IOR('o', 69, fe_status_t)
381#define FE_READ_BER _IOR('o', 70, __u32)
382#define FE_READ_SIGNAL_STRENGTH _IOR('o', 71, __u16)
383#define FE_READ_SNR _IOR('o', 72, __u16)
384#define FE_READ_UNCORRECTED_BLOCKS _IOR('o', 73, __u32)
385#define FE_SET_FRONTEND_TUNE_MODE _IO('o', 81)
386#define FE_GET_EVENT _IOR('o', 78, struct dvb_frontend_event)
387#define FE_DISHNETWORK_SEND_LEGACY_CMD _IO('o', 80)
388#define FE_SET_PROPERTY _IOW('o', 82, struct dtv_properties)
389#define FE_GET_PROPERTY _IOR('o', 83, struct dtv_properties)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800390enum fe_bandwidth {
391 BANDWIDTH_8_MHZ,
392 BANDWIDTH_7_MHZ,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800393 BANDWIDTH_6_MHZ,
394 BANDWIDTH_AUTO,
395 BANDWIDTH_5_MHZ,
396 BANDWIDTH_10_MHZ,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800397 BANDWIDTH_1_712_MHZ,
398};
399typedef enum fe_sec_voltage fe_sec_voltage_t;
400typedef enum fe_caps fe_caps_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800401typedef enum fe_type fe_type_t;
402typedef enum fe_sec_tone_mode fe_sec_tone_mode_t;
403typedef enum fe_sec_mini_cmd fe_sec_mini_cmd_t;
404typedef enum fe_status fe_status_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800405typedef enum fe_spectral_inversion fe_spectral_inversion_t;
406typedef enum fe_code_rate fe_code_rate_t;
407typedef enum fe_modulation fe_modulation_t;
408typedef enum fe_transmit_mode fe_transmit_mode_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800409typedef enum fe_bandwidth fe_bandwidth_t;
410typedef enum fe_guard_interval fe_guard_interval_t;
411typedef enum fe_hierarchy fe_hierarchy_t;
412typedef enum fe_pilot fe_pilot_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800413typedef enum fe_rolloff fe_rolloff_t;
414typedef enum fe_delivery_system fe_delivery_system_t;
415struct dvb_qpsk_parameters {
416 __u32 symbol_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800417 fe_code_rate_t fec_inner;
418};
419struct dvb_qam_parameters {
420 __u32 symbol_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800421 fe_code_rate_t fec_inner;
422 fe_modulation_t modulation;
423};
424struct dvb_vsb_parameters {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800425 fe_modulation_t modulation;
426};
427struct dvb_ofdm_parameters {
428 fe_bandwidth_t bandwidth;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800429 fe_code_rate_t code_rate_HP;
430 fe_code_rate_t code_rate_LP;
431 fe_modulation_t constellation;
432 fe_transmit_mode_t transmission_mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800433 fe_guard_interval_t guard_interval;
434 fe_hierarchy_t hierarchy_information;
435};
436struct dvb_frontend_parameters {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800437 __u32 frequency;
438 fe_spectral_inversion_t inversion;
439 union {
440 struct dvb_qpsk_parameters qpsk;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800441 struct dvb_qam_parameters qam;
442 struct dvb_ofdm_parameters ofdm;
443 struct dvb_vsb_parameters vsb;
444 } u;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800445};
446struct dvb_frontend_event {
447 fe_status_t status;
448 struct dvb_frontend_parameters parameters;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800449};
Ben Cheng655a7c02013-10-16 16:09:24 -0700450#define FE_SET_FRONTEND _IOW('o', 76, struct dvb_frontend_parameters)
451#define FE_GET_FRONTEND _IOR('o', 77, struct dvb_frontend_parameters)
Ben Cheng655a7c02013-10-16 16:09:24 -0700452#endif