blob: d060138f5d45e0ef990713ec53b5a75d19676326 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DVBFRONTEND_H_
20#define _DVBFRONTEND_H_
21#include <linux/types.h>
Christopher Ferris05d08e92016-02-04 13:16:38 -080022enum fe_caps {
Tao Baod7db5942015-01-28 10:07:51 -080023 FE_IS_STUPID = 0,
24 FE_CAN_INVERSION_AUTO = 0x1,
Tao Baod7db5942015-01-28 10:07:51 -080025 FE_CAN_FEC_1_2 = 0x2,
26 FE_CAN_FEC_2_3 = 0x4,
27 FE_CAN_FEC_3_4 = 0x8,
28 FE_CAN_FEC_4_5 = 0x10,
Tao Baod7db5942015-01-28 10:07:51 -080029 FE_CAN_FEC_5_6 = 0x20,
30 FE_CAN_FEC_6_7 = 0x40,
31 FE_CAN_FEC_7_8 = 0x80,
32 FE_CAN_FEC_8_9 = 0x100,
Tao Baod7db5942015-01-28 10:07:51 -080033 FE_CAN_FEC_AUTO = 0x200,
34 FE_CAN_QPSK = 0x400,
35 FE_CAN_QAM_16 = 0x800,
36 FE_CAN_QAM_32 = 0x1000,
Tao Baod7db5942015-01-28 10:07:51 -080037 FE_CAN_QAM_64 = 0x2000,
38 FE_CAN_QAM_128 = 0x4000,
39 FE_CAN_QAM_256 = 0x8000,
40 FE_CAN_QAM_AUTO = 0x10000,
Tao Baod7db5942015-01-28 10:07:51 -080041 FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000,
42 FE_CAN_BANDWIDTH_AUTO = 0x40000,
43 FE_CAN_GUARD_INTERVAL_AUTO = 0x80000,
44 FE_CAN_HIERARCHY_AUTO = 0x100000,
Tao Baod7db5942015-01-28 10:07:51 -080045 FE_CAN_8VSB = 0x200000,
46 FE_CAN_16VSB = 0x400000,
47 FE_HAS_EXTENDED_CAPS = 0x800000,
48 FE_CAN_MULTISTREAM = 0x4000000,
Tao Baod7db5942015-01-28 10:07:51 -080049 FE_CAN_TURBO_FEC = 0x8000000,
50 FE_CAN_2G_MODULATION = 0x10000000,
51 FE_NEEDS_BENDING = 0x20000000,
52 FE_CAN_RECOVER = 0x40000000,
Tao Baod7db5942015-01-28 10:07:51 -080053 FE_CAN_MUTE_TS = 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080054};
Christopher Ferris1308ad32017-11-14 17:32:13 -080055enum fe_type {
56 FE_QPSK,
57 FE_QAM,
58 FE_OFDM,
59 FE_ATSC
60};
Ben Cheng655a7c02013-10-16 16:09:24 -070061struct dvb_frontend_info {
Tao Baod7db5942015-01-28 10:07:51 -080062 char name[128];
Christopher Ferris05d08e92016-02-04 13:16:38 -080063 enum fe_type type;
Tao Baod7db5942015-01-28 10:07:51 -080064 __u32 frequency_min;
65 __u32 frequency_max;
66 __u32 frequency_stepsize;
Tao Baod7db5942015-01-28 10:07:51 -080067 __u32 frequency_tolerance;
68 __u32 symbol_rate_min;
69 __u32 symbol_rate_max;
70 __u32 symbol_rate_tolerance;
Tao Baod7db5942015-01-28 10:07:51 -080071 __u32 notifier_delay;
Christopher Ferris05d08e92016-02-04 13:16:38 -080072 enum fe_caps caps;
Ben Cheng655a7c02013-10-16 16:09:24 -070073};
74struct dvb_diseqc_master_cmd {
Tao Baod7db5942015-01-28 10:07:51 -080075 __u8 msg[6];
76 __u8 msg_len;
Ben Cheng655a7c02013-10-16 16:09:24 -070077};
78struct dvb_diseqc_slave_reply {
Tao Baod7db5942015-01-28 10:07:51 -080079 __u8 msg[4];
80 __u8 msg_len;
81 int timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -070082};
Christopher Ferris05d08e92016-02-04 13:16:38 -080083enum fe_sec_voltage {
Tao Baod7db5942015-01-28 10:07:51 -080084 SEC_VOLTAGE_13,
85 SEC_VOLTAGE_18,
86 SEC_VOLTAGE_OFF
Christopher Ferris05d08e92016-02-04 13:16:38 -080087};
88enum fe_sec_tone_mode {
Tao Baod7db5942015-01-28 10:07:51 -080089 SEC_TONE_ON,
90 SEC_TONE_OFF
Christopher Ferris05d08e92016-02-04 13:16:38 -080091};
92enum fe_sec_mini_cmd {
Tao Baod7db5942015-01-28 10:07:51 -080093 SEC_MINI_A,
94 SEC_MINI_B
Christopher Ferris05d08e92016-02-04 13:16:38 -080095};
96enum fe_status {
Christopher Ferris1308ad32017-11-14 17:32:13 -080097 FE_NONE = 0x00,
Tao Baod7db5942015-01-28 10:07:51 -080098 FE_HAS_SIGNAL = 0x01,
99 FE_HAS_CARRIER = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800100 FE_HAS_VITERBI = 0x04,
101 FE_HAS_SYNC = 0x08,
102 FE_HAS_LOCK = 0x10,
103 FE_TIMEDOUT = 0x20,
Tao Baod7db5942015-01-28 10:07:51 -0800104 FE_REINIT = 0x40,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800105};
106enum fe_spectral_inversion {
Tao Baod7db5942015-01-28 10:07:51 -0800107 INVERSION_OFF,
Tao Baod7db5942015-01-28 10:07:51 -0800108 INVERSION_ON,
109 INVERSION_AUTO
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110};
111enum fe_code_rate {
Tao Baod7db5942015-01-28 10:07:51 -0800112 FEC_NONE = 0,
113 FEC_1_2,
114 FEC_2_3,
115 FEC_3_4,
Tao Baod7db5942015-01-28 10:07:51 -0800116 FEC_4_5,
117 FEC_5_6,
118 FEC_6_7,
119 FEC_7_8,
Tao Baod7db5942015-01-28 10:07:51 -0800120 FEC_8_9,
121 FEC_AUTO,
122 FEC_3_5,
123 FEC_9_10,
Tao Baod7db5942015-01-28 10:07:51 -0800124 FEC_2_5,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800125};
126enum fe_modulation {
Tao Baod7db5942015-01-28 10:07:51 -0800127 QPSK,
Tao Baod7db5942015-01-28 10:07:51 -0800128 QAM_16,
129 QAM_32,
130 QAM_64,
131 QAM_128,
Tao Baod7db5942015-01-28 10:07:51 -0800132 QAM_256,
133 QAM_AUTO,
134 VSB_8,
135 VSB_16,
Tao Baod7db5942015-01-28 10:07:51 -0800136 PSK_8,
137 APSK_16,
138 APSK_32,
139 DQPSK,
Tao Baod7db5942015-01-28 10:07:51 -0800140 QAM_4_NR,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141};
142enum fe_transmit_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800143 TRANSMISSION_MODE_2K,
Tao Baod7db5942015-01-28 10:07:51 -0800144 TRANSMISSION_MODE_8K,
145 TRANSMISSION_MODE_AUTO,
146 TRANSMISSION_MODE_4K,
147 TRANSMISSION_MODE_1K,
Tao Baod7db5942015-01-28 10:07:51 -0800148 TRANSMISSION_MODE_16K,
149 TRANSMISSION_MODE_32K,
150 TRANSMISSION_MODE_C1,
151 TRANSMISSION_MODE_C3780,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800152};
153enum fe_guard_interval {
Tao Baod7db5942015-01-28 10:07:51 -0800154 GUARD_INTERVAL_1_32,
Tao Baod7db5942015-01-28 10:07:51 -0800155 GUARD_INTERVAL_1_16,
156 GUARD_INTERVAL_1_8,
157 GUARD_INTERVAL_1_4,
158 GUARD_INTERVAL_AUTO,
Tao Baod7db5942015-01-28 10:07:51 -0800159 GUARD_INTERVAL_1_128,
160 GUARD_INTERVAL_19_128,
161 GUARD_INTERVAL_19_256,
162 GUARD_INTERVAL_PN420,
Tao Baod7db5942015-01-28 10:07:51 -0800163 GUARD_INTERVAL_PN595,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800164 GUARD_INTERVAL_PN945,
165};
166enum fe_hierarchy {
Tao Baod7db5942015-01-28 10:07:51 -0800167 HIERARCHY_NONE,
168 HIERARCHY_1,
169 HIERARCHY_2,
170 HIERARCHY_4,
Tao Baod7db5942015-01-28 10:07:51 -0800171 HIERARCHY_AUTO
Christopher Ferris05d08e92016-02-04 13:16:38 -0800172};
Ben Cheng655a7c02013-10-16 16:09:24 -0700173enum fe_interleaving {
Tao Baod7db5942015-01-28 10:07:51 -0800174 INTERLEAVING_NONE,
Tao Baod7db5942015-01-28 10:07:51 -0800175 INTERLEAVING_AUTO,
176 INTERLEAVING_240,
177 INTERLEAVING_720,
Ben Cheng655a7c02013-10-16 16:09:24 -0700178};
Ben Cheng655a7c02013-10-16 16:09:24 -0700179#define DTV_UNDEFINED 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700180#define DTV_TUNE 1
181#define DTV_CLEAR 2
182#define DTV_FREQUENCY 3
183#define DTV_MODULATION 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700184#define DTV_BANDWIDTH_HZ 5
185#define DTV_INVERSION 6
186#define DTV_DISEQC_MASTER 7
187#define DTV_SYMBOL_RATE 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700188#define DTV_INNER_FEC 9
189#define DTV_VOLTAGE 10
190#define DTV_TONE 11
191#define DTV_PILOT 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700192#define DTV_ROLLOFF 13
193#define DTV_DISEQC_SLAVE_REPLY 14
194#define DTV_FE_CAPABILITY_COUNT 15
195#define DTV_FE_CAPABILITY 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700196#define DTV_DELIVERY_SYSTEM 17
197#define DTV_ISDBT_PARTIAL_RECEPTION 18
198#define DTV_ISDBT_SOUND_BROADCASTING 19
199#define DTV_ISDBT_SB_SUBCHANNEL_ID 20
Ben Cheng655a7c02013-10-16 16:09:24 -0700200#define DTV_ISDBT_SB_SEGMENT_IDX 21
201#define DTV_ISDBT_SB_SEGMENT_COUNT 22
202#define DTV_ISDBT_LAYERA_FEC 23
203#define DTV_ISDBT_LAYERA_MODULATION 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700204#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25
205#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26
206#define DTV_ISDBT_LAYERB_FEC 27
207#define DTV_ISDBT_LAYERB_MODULATION 28
Ben Cheng655a7c02013-10-16 16:09:24 -0700208#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29
209#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30
210#define DTV_ISDBT_LAYERC_FEC 31
211#define DTV_ISDBT_LAYERC_MODULATION 32
Ben Cheng655a7c02013-10-16 16:09:24 -0700212#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33
213#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34
214#define DTV_API_VERSION 35
215#define DTV_CODE_RATE_HP 36
Ben Cheng655a7c02013-10-16 16:09:24 -0700216#define DTV_CODE_RATE_LP 37
217#define DTV_GUARD_INTERVAL 38
218#define DTV_TRANSMISSION_MODE 39
219#define DTV_HIERARCHY 40
Ben Cheng655a7c02013-10-16 16:09:24 -0700220#define DTV_ISDBT_LAYER_ENABLED 41
221#define DTV_STREAM_ID 42
222#define DTV_ISDBS_TS_ID_LEGACY DTV_STREAM_ID
223#define DTV_DVBT2_PLP_ID_LEGACY 43
Ben Cheng655a7c02013-10-16 16:09:24 -0700224#define DTV_ENUM_DELSYS 44
225#define DTV_ATSCMH_FIC_VER 45
226#define DTV_ATSCMH_PARADE_ID 46
227#define DTV_ATSCMH_NOG 47
Ben Cheng655a7c02013-10-16 16:09:24 -0700228#define DTV_ATSCMH_TNOG 48
229#define DTV_ATSCMH_SGN 49
230#define DTV_ATSCMH_PRC 50
231#define DTV_ATSCMH_RS_FRAME_MODE 51
Ben Cheng655a7c02013-10-16 16:09:24 -0700232#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52
233#define DTV_ATSCMH_RS_CODE_MODE_PRI 53
234#define DTV_ATSCMH_RS_CODE_MODE_SEC 54
235#define DTV_ATSCMH_SCCC_BLOCK_MODE 55
Ben Cheng655a7c02013-10-16 16:09:24 -0700236#define DTV_ATSCMH_SCCC_CODE_MODE_A 56
237#define DTV_ATSCMH_SCCC_CODE_MODE_B 57
238#define DTV_ATSCMH_SCCC_CODE_MODE_C 58
239#define DTV_ATSCMH_SCCC_CODE_MODE_D 59
Ben Cheng655a7c02013-10-16 16:09:24 -0700240#define DTV_INTERLEAVING 60
241#define DTV_LNA 61
242#define DTV_STAT_SIGNAL_STRENGTH 62
243#define DTV_STAT_CNR 63
Ben Cheng655a7c02013-10-16 16:09:24 -0700244#define DTV_STAT_PRE_ERROR_BIT_COUNT 64
245#define DTV_STAT_PRE_TOTAL_BIT_COUNT 65
246#define DTV_STAT_POST_ERROR_BIT_COUNT 66
247#define DTV_STAT_POST_TOTAL_BIT_COUNT 67
Ben Cheng655a7c02013-10-16 16:09:24 -0700248#define DTV_STAT_ERROR_BLOCK_COUNT 68
249#define DTV_STAT_TOTAL_BLOCK_COUNT 69
Christopher Ferris76a1d452018-06-27 14:12:29 -0700250#define DTV_SCRAMBLING_SEQUENCE_INDEX 70
251#define DTV_MAX_COMMAND DTV_SCRAMBLING_SEQUENCE_INDEX
Christopher Ferris05d08e92016-02-04 13:16:38 -0800252enum fe_pilot {
Tao Baod7db5942015-01-28 10:07:51 -0800253 PILOT_ON,
254 PILOT_OFF,
255 PILOT_AUTO,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800256};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800257enum fe_rolloff {
Tao Baod7db5942015-01-28 10:07:51 -0800258 ROLLOFF_35,
259 ROLLOFF_20,
260 ROLLOFF_25,
Tao Baod7db5942015-01-28 10:07:51 -0800261 ROLLOFF_AUTO,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800262};
263enum fe_delivery_system {
Tao Baod7db5942015-01-28 10:07:51 -0800264 SYS_UNDEFINED,
Tao Baod7db5942015-01-28 10:07:51 -0800265 SYS_DVBC_ANNEX_A,
266 SYS_DVBC_ANNEX_B,
267 SYS_DVBT,
268 SYS_DSS,
Tao Baod7db5942015-01-28 10:07:51 -0800269 SYS_DVBS,
270 SYS_DVBS2,
271 SYS_DVBH,
272 SYS_ISDBT,
Tao Baod7db5942015-01-28 10:07:51 -0800273 SYS_ISDBS,
274 SYS_ISDBC,
275 SYS_ATSC,
276 SYS_ATSCMH,
Tao Baod7db5942015-01-28 10:07:51 -0800277 SYS_DTMB,
278 SYS_CMMB,
279 SYS_DAB,
280 SYS_DVBT2,
Tao Baod7db5942015-01-28 10:07:51 -0800281 SYS_TURBO,
282 SYS_DVBC_ANNEX_C,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800283};
Ben Cheng655a7c02013-10-16 16:09:24 -0700284#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A
Ben Cheng655a7c02013-10-16 16:09:24 -0700285#define SYS_DMBTH SYS_DTMB
286enum atscmh_sccc_block_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800287 ATSCMH_SCCC_BLK_SEP = 0,
288 ATSCMH_SCCC_BLK_COMB = 1,
Tao Baod7db5942015-01-28 10:07:51 -0800289 ATSCMH_SCCC_BLK_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700290};
291enum atscmh_sccc_code_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800292 ATSCMH_SCCC_CODE_HLF = 0,
Tao Baod7db5942015-01-28 10:07:51 -0800293 ATSCMH_SCCC_CODE_QTR = 1,
294 ATSCMH_SCCC_CODE_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700295};
296enum atscmh_rs_frame_ensemble {
Tao Baod7db5942015-01-28 10:07:51 -0800297 ATSCMH_RSFRAME_ENS_PRI = 0,
298 ATSCMH_RSFRAME_ENS_SEC = 1,
Ben Cheng655a7c02013-10-16 16:09:24 -0700299};
300enum atscmh_rs_frame_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800301 ATSCMH_RSFRAME_PRI_ONLY = 0,
302 ATSCMH_RSFRAME_PRI_SEC = 1,
303 ATSCMH_RSFRAME_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700304};
Ben Cheng655a7c02013-10-16 16:09:24 -0700305enum atscmh_rs_code_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800306 ATSCMH_RSCODE_211_187 = 0,
307 ATSCMH_RSCODE_223_187 = 1,
308 ATSCMH_RSCODE_235_187 = 2,
Tao Baod7db5942015-01-28 10:07:51 -0800309 ATSCMH_RSCODE_RES = 3,
Ben Cheng655a7c02013-10-16 16:09:24 -0700310};
311#define NO_STREAM_ID_FILTER (~0U)
312#define LNA_AUTO (~0U)
Ben Cheng655a7c02013-10-16 16:09:24 -0700313enum fecap_scale_params {
Tao Baod7db5942015-01-28 10:07:51 -0800314 FE_SCALE_NOT_AVAILABLE = 0,
315 FE_SCALE_DECIBEL,
316 FE_SCALE_RELATIVE,
317 FE_SCALE_COUNTER
Ben Cheng655a7c02013-10-16 16:09:24 -0700318};
319struct dtv_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800320 __u8 scale;
321 union {
Tao Baod7db5942015-01-28 10:07:51 -0800322 __u64 uvalue;
323 __s64 svalue;
324 };
325} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700326#define MAX_DTV_STATS 4
327struct dtv_fe_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800328 __u8 len;
329 struct dtv_stats stat[MAX_DTV_STATS];
Tao Baod7db5942015-01-28 10:07:51 -0800330} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700331struct dtv_property {
Tao Baod7db5942015-01-28 10:07:51 -0800332 __u32 cmd;
333 __u32 reserved[3];
Tao Baod7db5942015-01-28 10:07:51 -0800334 union {
335 __u32 data;
336 struct dtv_fe_stats st;
337 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800338 __u8 data[32];
339 __u32 len;
340 __u32 reserved1[3];
341 void * reserved2;
Tao Baod7db5942015-01-28 10:07:51 -0800342 } buffer;
343 } u;
344 int result;
345} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700346#define DTV_IOCTL_MAX_MSGS 64
347struct dtv_properties {
Tao Baod7db5942015-01-28 10:07:51 -0800348 __u32 num;
349 struct dtv_property * props;
Ben Cheng655a7c02013-10-16 16:09:24 -0700350};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800351#define FE_TUNE_MODE_ONESHOT 0x01
352#define FE_GET_INFO _IOR('o', 61, struct dvb_frontend_info)
353#define FE_DISEQC_RESET_OVERLOAD _IO('o', 62)
354#define FE_DISEQC_SEND_MASTER_CMD _IOW('o', 63, struct dvb_diseqc_master_cmd)
355#define FE_DISEQC_RECV_SLAVE_REPLY _IOR('o', 64, struct dvb_diseqc_slave_reply)
356#define FE_DISEQC_SEND_BURST _IO('o', 65)
357#define FE_SET_TONE _IO('o', 66)
358#define FE_SET_VOLTAGE _IO('o', 67)
359#define FE_ENABLE_HIGH_LNB_VOLTAGE _IO('o', 68)
360#define FE_READ_STATUS _IOR('o', 69, fe_status_t)
361#define FE_READ_BER _IOR('o', 70, __u32)
362#define FE_READ_SIGNAL_STRENGTH _IOR('o', 71, __u16)
363#define FE_READ_SNR _IOR('o', 72, __u16)
364#define FE_READ_UNCORRECTED_BLOCKS _IOR('o', 73, __u32)
365#define FE_SET_FRONTEND_TUNE_MODE _IO('o', 81)
366#define FE_GET_EVENT _IOR('o', 78, struct dvb_frontend_event)
367#define FE_DISHNETWORK_SEND_LEGACY_CMD _IO('o', 80)
368#define FE_SET_PROPERTY _IOW('o', 82, struct dtv_properties)
369#define FE_GET_PROPERTY _IOR('o', 83, struct dtv_properties)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800370enum fe_bandwidth {
371 BANDWIDTH_8_MHZ,
372 BANDWIDTH_7_MHZ,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800373 BANDWIDTH_6_MHZ,
374 BANDWIDTH_AUTO,
375 BANDWIDTH_5_MHZ,
376 BANDWIDTH_10_MHZ,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800377 BANDWIDTH_1_712_MHZ,
378};
379typedef enum fe_sec_voltage fe_sec_voltage_t;
380typedef enum fe_caps fe_caps_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800381typedef enum fe_type fe_type_t;
382typedef enum fe_sec_tone_mode fe_sec_tone_mode_t;
383typedef enum fe_sec_mini_cmd fe_sec_mini_cmd_t;
384typedef enum fe_status fe_status_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800385typedef enum fe_spectral_inversion fe_spectral_inversion_t;
386typedef enum fe_code_rate fe_code_rate_t;
387typedef enum fe_modulation fe_modulation_t;
388typedef enum fe_transmit_mode fe_transmit_mode_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800389typedef enum fe_bandwidth fe_bandwidth_t;
390typedef enum fe_guard_interval fe_guard_interval_t;
391typedef enum fe_hierarchy fe_hierarchy_t;
392typedef enum fe_pilot fe_pilot_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800393typedef enum fe_rolloff fe_rolloff_t;
394typedef enum fe_delivery_system fe_delivery_system_t;
395struct dvb_qpsk_parameters {
396 __u32 symbol_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800397 fe_code_rate_t fec_inner;
398};
399struct dvb_qam_parameters {
400 __u32 symbol_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800401 fe_code_rate_t fec_inner;
402 fe_modulation_t modulation;
403};
404struct dvb_vsb_parameters {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800405 fe_modulation_t modulation;
406};
407struct dvb_ofdm_parameters {
408 fe_bandwidth_t bandwidth;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800409 fe_code_rate_t code_rate_HP;
410 fe_code_rate_t code_rate_LP;
411 fe_modulation_t constellation;
412 fe_transmit_mode_t transmission_mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800413 fe_guard_interval_t guard_interval;
414 fe_hierarchy_t hierarchy_information;
415};
416struct dvb_frontend_parameters {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800417 __u32 frequency;
418 fe_spectral_inversion_t inversion;
419 union {
420 struct dvb_qpsk_parameters qpsk;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800421 struct dvb_qam_parameters qam;
422 struct dvb_ofdm_parameters ofdm;
423 struct dvb_vsb_parameters vsb;
424 } u;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800425};
426struct dvb_frontend_event {
427 fe_status_t status;
428 struct dvb_frontend_parameters parameters;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800429};
Ben Cheng655a7c02013-10-16 16:09:24 -0700430#define FE_SET_FRONTEND _IOW('o', 76, struct dvb_frontend_parameters)
431#define FE_GET_FRONTEND _IOR('o', 77, struct dvb_frontend_parameters)
Ben Cheng655a7c02013-10-16 16:09:24 -0700432#endif