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gerrit.omnirom.org / android_bionic / 2c0e9a58ead53aff66f0978c51142d8331ffffb0 / . / libc / kernel / uapi / sound / skl-tplg-interface.h
blob: c62029595ed76a00d64dac2d4f944cdc98b9ef53 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]7#ifndef __HDA_TPLG_INTERFACE_H__
8#define __HDA_TPLG_INTERFACE_H__
9#include <linux/types.h>
10#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
11#define SKL_CONTROL_TYPE_MIC_SELECT 0x102
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700[diff] [blame]12#define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x103
13#define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x104
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]14#define HDA_SST_CFG_MAX 900
15#define MAX_IN_QUEUE 8
16#define MAX_OUT_QUEUE 8
17#define SKL_UUID_STR_SZ 40
18enum skl_event_types {
19 SKL_EVENT_NONE = 0,
20 SKL_MIXER_EVENT,
21 SKL_MUX_EVENT,
22 SKL_VMIXER_EVENT,
23 SKL_PGA_EVENT
24};
25enum skl_ch_cfg {
26 SKL_CH_CFG_MONO = 0,
27 SKL_CH_CFG_STEREO = 1,
28 SKL_CH_CFG_2_1 = 2,
29 SKL_CH_CFG_3_0 = 3,
30 SKL_CH_CFG_3_1 = 4,
31 SKL_CH_CFG_QUATRO = 5,
32 SKL_CH_CFG_4_0 = 6,
33 SKL_CH_CFG_5_0 = 7,
34 SKL_CH_CFG_5_1 = 8,
35 SKL_CH_CFG_DUAL_MONO = 9,
36 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
37 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700[diff] [blame]38 SKL_CH_CFG_7_1 = 12,
39 SKL_CH_CFG_4_CHANNEL = SKL_CH_CFG_7_1,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]40 SKL_CH_CFG_INVALID
41};
42enum skl_module_type {
43 SKL_MODULE_TYPE_MIXER = 0,
44 SKL_MODULE_TYPE_COPIER,
45 SKL_MODULE_TYPE_UPDWMIX,
46 SKL_MODULE_TYPE_SRCINT,
47 SKL_MODULE_TYPE_ALGO,
48 SKL_MODULE_TYPE_BASE_OUTFMT,
49 SKL_MODULE_TYPE_KPB,
50 SKL_MODULE_TYPE_MIC_SELECT,
51};
52enum skl_core_affinity {
53 SKL_AFFINITY_CORE_0 = 0,
54 SKL_AFFINITY_CORE_1,
55 SKL_AFFINITY_CORE_MAX
56};
57enum skl_pipe_conn_type {
58 SKL_PIPE_CONN_TYPE_NONE = 0,
59 SKL_PIPE_CONN_TYPE_FE,
60 SKL_PIPE_CONN_TYPE_BE
61};
62enum skl_hw_conn_type {
63 SKL_CONN_NONE = 0,
64 SKL_CONN_SOURCE = 1,
65 SKL_CONN_SINK = 2
66};
67enum skl_dev_type {
68 SKL_DEVICE_BT = 0x0,
69 SKL_DEVICE_DMIC = 0x1,
70 SKL_DEVICE_I2S = 0x2,
71 SKL_DEVICE_SLIMBUS = 0x3,
72 SKL_DEVICE_HDALINK = 0x4,
73 SKL_DEVICE_HDAHOST = 0x5,
74 SKL_DEVICE_NONE
75};
76enum skl_interleaving {
77 SKL_INTERLEAVING_PER_CHANNEL = 0,
78 SKL_INTERLEAVING_PER_SAMPLE = 1,
79};
80enum skl_sample_type {
81 SKL_SAMPLE_TYPE_INT_MSB = 0,
82 SKL_SAMPLE_TYPE_INT_LSB = 1,
83 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
84 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
85 SKL_SAMPLE_TYPE_FLOAT = 4
86};
87enum module_pin_type {
88 SKL_PIN_TYPE_HOMOGENEOUS,
89 SKL_PIN_TYPE_HETEROGENEOUS,
90};
91enum skl_module_param_type {
92 SKL_PARAM_DEFAULT = 0,
93 SKL_PARAM_INIT,
94 SKL_PARAM_SET,
95 SKL_PARAM_BIND
96};
97struct skl_dfw_algo_data {
98 __u32 set_params : 2;
99 __u32 rsvd : 30;
100 __u32 param_id;
101 __u32 max;
Christopher Ferris7447a1c2022-10-04 18:24:44 -0700[diff] [blame]102 char params[];
Colin Cross4ac33222022-12-15 15:45:35 -0800[diff] [blame]103} __attribute__((__packed__));
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]104enum skl_tkn_dir {
105 SKL_DIR_IN,
106 SKL_DIR_OUT
107};
108enum skl_tuple_type {
109 SKL_TYPE_TUPLE,
110 SKL_TYPE_DATA
111};
112struct skl_dfw_v4_module_pin {
113 __u16 module_id;
114 __u16 instance_id;
Colin Cross4ac33222022-12-15 15:45:35 -0800[diff] [blame]115} __attribute__((__packed__));
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]116struct skl_dfw_v4_module_fmt {
117 __u32 channels;
118 __u32 freq;
119 __u32 bit_depth;
120 __u32 valid_bit_depth;
121 __u32 ch_cfg;
122 __u32 interleaving_style;
123 __u32 sample_type;
124 __u32 ch_map;
Colin Cross4ac33222022-12-15 15:45:35 -0800[diff] [blame]125} __attribute__((__packed__));
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]126struct skl_dfw_v4_module_caps {
127 __u32 set_params : 2;
128 __u32 rsvd : 30;
129 __u32 param_id;
130 __u32 caps_size;
131 __u32 caps[HDA_SST_CFG_MAX];
Colin Cross4ac33222022-12-15 15:45:35 -0800[diff] [blame]132} __attribute__((__packed__));
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]133struct skl_dfw_v4_pipe {
134 __u8 pipe_id;
135 __u8 pipe_priority;
136 __u16 conn_type : 4;
137 __u16 rsvd : 4;
138 __u16 memory_pages : 8;
Colin Cross4ac33222022-12-15 15:45:35 -0800[diff] [blame]139} __attribute__((__packed__));
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]140struct skl_dfw_v4_module {
141 char uuid[SKL_UUID_STR_SZ];
142 __u16 module_id;
143 __u16 instance_id;
144 __u32 max_mcps;
145 __u32 mem_pages;
146 __u32 obs;
147 __u32 ibs;
148 __u32 vbus_id;
149 __u32 max_in_queue : 8;
150 __u32 max_out_queue : 8;
151 __u32 time_slot : 8;
152 __u32 core_id : 4;
153 __u32 rsvd1 : 4;
154 __u32 module_type : 8;
155 __u32 conn_type : 4;
156 __u32 dev_type : 4;
157 __u32 hw_conn_type : 4;
158 __u32 rsvd2 : 12;
159 __u32 params_fixup : 8;
160 __u32 converter : 8;
161 __u32 input_pin_type : 1;
162 __u32 output_pin_type : 1;
163 __u32 is_dynamic_in_pin : 1;
164 __u32 is_dynamic_out_pin : 1;
165 __u32 is_loadable : 1;
166 __u32 rsvd3 : 11;
167 struct skl_dfw_v4_pipe pipe;
168 struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
169 struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
170 struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
171 struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
172 struct skl_dfw_v4_module_caps caps;
Colin Cross4ac33222022-12-15 15:45:35 -0800[diff] [blame]173} __attribute__((__packed__));
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]174#endif