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gerrit.omnirom.org / android_bionic / 9ce28844db7cf80ee8cf7c88dab23b666eaab739 / . / libc / kernel / uapi / sound / skl-tplg-interface.h
blob: 58e0afa5975248785890226b69b516808f4d6a38 [file] [log] [blame]
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame^]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __HDA_TPLG_INTERFACE_H__
20#define __HDA_TPLG_INTERFACE_H__
21#include <linux/types.h>
22#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
23#define SKL_CONTROL_TYPE_MIC_SELECT 0x102
24#define HDA_SST_CFG_MAX 900
25#define MAX_IN_QUEUE 8
26#define MAX_OUT_QUEUE 8
27#define SKL_UUID_STR_SZ 40
28enum skl_event_types {
29 SKL_EVENT_NONE = 0,
30 SKL_MIXER_EVENT,
31 SKL_MUX_EVENT,
32 SKL_VMIXER_EVENT,
33 SKL_PGA_EVENT
34};
35enum skl_ch_cfg {
36 SKL_CH_CFG_MONO = 0,
37 SKL_CH_CFG_STEREO = 1,
38 SKL_CH_CFG_2_1 = 2,
39 SKL_CH_CFG_3_0 = 3,
40 SKL_CH_CFG_3_1 = 4,
41 SKL_CH_CFG_QUATRO = 5,
42 SKL_CH_CFG_4_0 = 6,
43 SKL_CH_CFG_5_0 = 7,
44 SKL_CH_CFG_5_1 = 8,
45 SKL_CH_CFG_DUAL_MONO = 9,
46 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
47 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
48 SKL_CH_CFG_4_CHANNEL = 12,
49 SKL_CH_CFG_INVALID
50};
51enum skl_module_type {
52 SKL_MODULE_TYPE_MIXER = 0,
53 SKL_MODULE_TYPE_COPIER,
54 SKL_MODULE_TYPE_UPDWMIX,
55 SKL_MODULE_TYPE_SRCINT,
56 SKL_MODULE_TYPE_ALGO,
57 SKL_MODULE_TYPE_BASE_OUTFMT,
58 SKL_MODULE_TYPE_KPB,
59 SKL_MODULE_TYPE_MIC_SELECT,
60};
61enum skl_core_affinity {
62 SKL_AFFINITY_CORE_0 = 0,
63 SKL_AFFINITY_CORE_1,
64 SKL_AFFINITY_CORE_MAX
65};
66enum skl_pipe_conn_type {
67 SKL_PIPE_CONN_TYPE_NONE = 0,
68 SKL_PIPE_CONN_TYPE_FE,
69 SKL_PIPE_CONN_TYPE_BE
70};
71enum skl_hw_conn_type {
72 SKL_CONN_NONE = 0,
73 SKL_CONN_SOURCE = 1,
74 SKL_CONN_SINK = 2
75};
76enum skl_dev_type {
77 SKL_DEVICE_BT = 0x0,
78 SKL_DEVICE_DMIC = 0x1,
79 SKL_DEVICE_I2S = 0x2,
80 SKL_DEVICE_SLIMBUS = 0x3,
81 SKL_DEVICE_HDALINK = 0x4,
82 SKL_DEVICE_HDAHOST = 0x5,
83 SKL_DEVICE_NONE
84};
85enum skl_interleaving {
86 SKL_INTERLEAVING_PER_CHANNEL = 0,
87 SKL_INTERLEAVING_PER_SAMPLE = 1,
88};
89enum skl_sample_type {
90 SKL_SAMPLE_TYPE_INT_MSB = 0,
91 SKL_SAMPLE_TYPE_INT_LSB = 1,
92 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
93 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
94 SKL_SAMPLE_TYPE_FLOAT = 4
95};
96enum module_pin_type {
97 SKL_PIN_TYPE_HOMOGENEOUS,
98 SKL_PIN_TYPE_HETEROGENEOUS,
99};
100enum skl_module_param_type {
101 SKL_PARAM_DEFAULT = 0,
102 SKL_PARAM_INIT,
103 SKL_PARAM_SET,
104 SKL_PARAM_BIND
105};
106struct skl_dfw_algo_data {
107 __u32 set_params : 2;
108 __u32 rsvd : 30;
109 __u32 param_id;
110 __u32 max;
111 char params[0];
112} __packed;
113enum skl_tkn_dir {
114 SKL_DIR_IN,
115 SKL_DIR_OUT
116};
117enum skl_tuple_type {
118 SKL_TYPE_TUPLE,
119 SKL_TYPE_DATA
120};
121struct skl_dfw_v4_module_pin {
122 __u16 module_id;
123 __u16 instance_id;
124} __packed;
125struct skl_dfw_v4_module_fmt {
126 __u32 channels;
127 __u32 freq;
128 __u32 bit_depth;
129 __u32 valid_bit_depth;
130 __u32 ch_cfg;
131 __u32 interleaving_style;
132 __u32 sample_type;
133 __u32 ch_map;
134} __packed;
135struct skl_dfw_v4_module_caps {
136 __u32 set_params : 2;
137 __u32 rsvd : 30;
138 __u32 param_id;
139 __u32 caps_size;
140 __u32 caps[HDA_SST_CFG_MAX];
141} __packed;
142struct skl_dfw_v4_pipe {
143 __u8 pipe_id;
144 __u8 pipe_priority;
145 __u16 conn_type : 4;
146 __u16 rsvd : 4;
147 __u16 memory_pages : 8;
148} __packed;
149struct skl_dfw_v4_module {
150 char uuid[SKL_UUID_STR_SZ];
151 __u16 module_id;
152 __u16 instance_id;
153 __u32 max_mcps;
154 __u32 mem_pages;
155 __u32 obs;
156 __u32 ibs;
157 __u32 vbus_id;
158 __u32 max_in_queue : 8;
159 __u32 max_out_queue : 8;
160 __u32 time_slot : 8;
161 __u32 core_id : 4;
162 __u32 rsvd1 : 4;
163 __u32 module_type : 8;
164 __u32 conn_type : 4;
165 __u32 dev_type : 4;
166 __u32 hw_conn_type : 4;
167 __u32 rsvd2 : 12;
168 __u32 params_fixup : 8;
169 __u32 converter : 8;
170 __u32 input_pin_type : 1;
171 __u32 output_pin_type : 1;
172 __u32 is_dynamic_in_pin : 1;
173 __u32 is_dynamic_out_pin : 1;
174 __u32 is_loadable : 1;
175 __u32 rsvd3 : 11;
176 struct skl_dfw_v4_pipe pipe;
177 struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
178 struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
179 struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
180 struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
181 struct skl_dfw_v4_module_caps caps;
182} __packed;
183#endif