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gerrit.omnirom.org / android_bionic / 180edefbd287c39caeb9d48784a9a10ac35f3636 / . / libc / kernel / uapi / drm / qxl_drm.h
blob: b2412343f85d14278bea8e470bfa0495a8b58b44 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame^]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]7#ifndef QXL_DRM_H
8#define QXL_DRM_H
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]9#include "drm.h"
10#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800[diff] [blame]11extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]12#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]13#define QXL_GEM_DOMAIN_CPU 0
14#define QXL_GEM_DOMAIN_VRAM 1
15#define QXL_GEM_DOMAIN_SURFACE 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]16#define DRM_QXL_ALLOC 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]17#define DRM_QXL_MAP 0x01
18#define DRM_QXL_EXECBUFFER 0x02
19#define DRM_QXL_UPDATE_AREA 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]20#define DRM_QXL_GETPARAM 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]21#define DRM_QXL_CLIENTCAP 0x05
22#define DRM_QXL_ALLOC_SURF 0x06
23struct drm_qxl_alloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]24 __u32 size;
25 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26};
27struct drm_qxl_map {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]28 __u64 offset;
29 __u32 handle;
30 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]32#define QXL_RELOC_TYPE_BO 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33#define QXL_RELOC_TYPE_SURF 2
34struct drm_qxl_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]35 __u64 src_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]36 __u64 dst_offset;
37 __u32 src_handle;
38 __u32 dst_handle;
39 __u32 reloc_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]40 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41};
42struct drm_qxl_command {
Christopher Ferris1308ad32017-11-14 17:32:13 -0800[diff] [blame]43 __u64 command;
44 __u64 relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]45 __u32 type;
46 __u32 command_size;
47 __u32 relocs_num;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]48 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49};
50struct drm_qxl_execbuffer {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]51 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]52 __u32 commands_num;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800[diff] [blame]53 __u64 commands;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54};
55struct drm_qxl_update_area {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]56 __u32 handle;
57 __u32 top;
58 __u32 left;
59 __u32 bottom;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]60 __u32 right;
61 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]62};
63#define QXL_PARAM_NUM_SURFACES 1
64#define QXL_PARAM_MAX_RELOCS 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65struct drm_qxl_getparam {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]66 __u64 param;
67 __u64 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]68};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69struct drm_qxl_clientcap {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]70 __u32 index;
71 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]72};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73struct drm_qxl_alloc_surf {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]74 __u32 format;
75 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]76 __u32 height;
77 __s32 stride;
78 __u32 handle;
79 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]81#define DRM_IOCTL_QXL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
82#define DRM_IOCTL_QXL_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
83#define DRM_IOCTL_QXL_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER, struct drm_qxl_execbuffer)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]84#define DRM_IOCTL_QXL_UPDATE_AREA DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA, struct drm_qxl_update_area)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]85#define DRM_IOCTL_QXL_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM, struct drm_qxl_getparam)
86#define DRM_IOCTL_QXL_CLIENTCAP DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP, struct drm_qxl_clientcap)
87#define DRM_IOCTL_QXL_ALLOC_SURF DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF, struct drm_qxl_alloc_surf)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]88#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800[diff] [blame]89}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]90#endif
91#endif