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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / qxl_drm.h
blob: 66364542a03b6392fb50409b7f3d155f38ebaa88 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef QXL_DRM_H
20#define QXL_DRM_H
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]21#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25#define QXL_GEM_DOMAIN_CPU 0
26#define QXL_GEM_DOMAIN_VRAM 1
27#define QXL_GEM_DOMAIN_SURFACE 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]29#define DRM_QXL_ALLOC 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30#define DRM_QXL_MAP 0x01
31#define DRM_QXL_EXECBUFFER 0x02
32#define DRM_QXL_UPDATE_AREA 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]34#define DRM_QXL_GETPARAM 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35#define DRM_QXL_CLIENTCAP 0x05
36#define DRM_QXL_ALLOC_SURF 0x06
37struct drm_qxl_alloc {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]39 __u32 size;
40 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41};
42struct drm_qxl_map {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]44 __u64 offset;
45 __u32 handle;
46 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]49#define QXL_RELOC_TYPE_BO 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50#define QXL_RELOC_TYPE_SURF 2
51struct drm_qxl_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]52 __u64 src_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]54 __u64 dst_offset;
55 __u32 src_handle;
56 __u32 dst_handle;
57 __u32 reloc_type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]59 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]60};
61struct drm_qxl_command {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]62 __u64 __user command;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]64 __u64 __user relocs;
65 __u32 type;
66 __u32 command_size;
67 __u32 relocs_num;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]69 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]70};
71struct drm_qxl_execbuffer {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]72 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]74 __u32 commands_num;
75 __u64 __user commands;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]76};
77struct drm_qxl_update_area {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]79 __u32 handle;
80 __u32 top;
81 __u32 left;
82 __u32 bottom;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]84 __u32 right;
85 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]86};
87#define QXL_PARAM_NUM_SURFACES 1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define QXL_PARAM_MAX_RELOCS 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90struct drm_qxl_getparam {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]91 __u64 param;
92 __u64 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]94};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95struct drm_qxl_clientcap {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]96 __u32 index;
97 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]99};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]100struct drm_qxl_alloc_surf {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]101 __u32 format;
102 __u32 width;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]104 __u32 height;
105 __s32 stride;
106 __u32 handle;
107 __u32 pad;
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110#define DRM_IOCTL_QXL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
111#define DRM_IOCTL_QXL_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
112#define DRM_IOCTL_QXL_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER, struct drm_qxl_execbuffer)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]114#define DRM_IOCTL_QXL_UPDATE_AREA DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA, struct drm_qxl_update_area)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]115#define DRM_IOCTL_QXL_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM, struct drm_qxl_getparam)
116#define DRM_IOCTL_QXL_CLIENTCAP DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP, struct drm_qxl_clientcap)
117#define DRM_IOCTL_QXL_ALLOC_SURF DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF, struct drm_qxl_alloc_surf)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]119#ifdef __cplusplus
120#endif
121#endif