blob: 2a3424ec524384ba3d108210da42badf4e72ceb8 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Elliott Hughes5e7f8f12022-10-01 15:10:58 +00007#ifndef __LINUX_KVM_RISCV_H
8#define __LINUX_KVM_RISCV_H
9#ifndef __ASSEMBLY__
10#include <linux/types.h>
Christopher Ferris37c3f3c2023-07-10 10:59:05 -070011#include <asm/bitsperlong.h>
Elliott Hughes5e7f8f12022-10-01 15:10:58 +000012#include <asm/ptrace.h>
Christopher Ferris8666d042023-09-06 14:55:31 -070013#define __KVM_HAVE_IRQ_LINE
Elliott Hughes5e7f8f12022-10-01 15:10:58 +000014#define __KVM_HAVE_READONLY_MEM
15#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
16#define KVM_INTERRUPT_SET - 1U
17#define KVM_INTERRUPT_UNSET - 2U
18struct kvm_regs {
19};
20struct kvm_fpu {
21};
22struct kvm_debug_exit_arch {
23};
24struct kvm_guest_debug_arch {
25};
26struct kvm_sync_regs {
27};
28struct kvm_sregs {
29};
30struct kvm_riscv_config {
31 unsigned long isa;
Christopher Ferris6cd53a52022-12-12 23:39:16 +000032 unsigned long zicbom_block_size;
Christopher Ferris8b7fdc92023-02-21 13:36:32 -080033 unsigned long mvendorid;
34 unsigned long marchid;
35 unsigned long mimpid;
Christopher Ferris37c3f3c2023-07-10 10:59:05 -070036 unsigned long zicboz_block_size;
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070037 unsigned long satp_mode;
Elliott Hughes5e7f8f12022-10-01 15:10:58 +000038};
39struct kvm_riscv_core {
40 struct user_regs_struct regs;
41 unsigned long mode;
42};
43#define KVM_RISCV_MODE_S 1
44#define KVM_RISCV_MODE_U 0
45struct kvm_riscv_csr {
46 unsigned long sstatus;
47 unsigned long sie;
48 unsigned long stvec;
49 unsigned long sscratch;
50 unsigned long sepc;
51 unsigned long scause;
52 unsigned long stval;
53 unsigned long sip;
54 unsigned long satp;
55 unsigned long scounteren;
56};
Christopher Ferris37c3f3c2023-07-10 10:59:05 -070057struct kvm_riscv_aia_csr {
58 unsigned long siselect;
59 unsigned long iprio1;
60 unsigned long iprio2;
61 unsigned long sieh;
62 unsigned long siph;
63 unsigned long iprio1h;
64 unsigned long iprio2h;
65};
Elliott Hughes5e7f8f12022-10-01 15:10:58 +000066struct kvm_riscv_timer {
67 __u64 frequency;
68 __u64 time;
69 __u64 compare;
70 __u64 state;
71};
72enum KVM_RISCV_ISA_EXT_ID {
73 KVM_RISCV_ISA_EXT_A = 0,
74 KVM_RISCV_ISA_EXT_C,
75 KVM_RISCV_ISA_EXT_D,
76 KVM_RISCV_ISA_EXT_F,
77 KVM_RISCV_ISA_EXT_H,
78 KVM_RISCV_ISA_EXT_I,
79 KVM_RISCV_ISA_EXT_M,
Christopher Ferris7447a1c2022-10-04 18:24:44 -070080 KVM_RISCV_ISA_EXT_SVPBMT,
81 KVM_RISCV_ISA_EXT_SSTC,
Christopher Ferris6cd53a52022-12-12 23:39:16 +000082 KVM_RISCV_ISA_EXT_SVINVAL,
83 KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
84 KVM_RISCV_ISA_EXT_ZICBOM,
Christopher Ferris37c3f3c2023-07-10 10:59:05 -070085 KVM_RISCV_ISA_EXT_ZICBOZ,
86 KVM_RISCV_ISA_EXT_ZBB,
87 KVM_RISCV_ISA_EXT_SSAIA,
Christopher Ferris8666d042023-09-06 14:55:31 -070088 KVM_RISCV_ISA_EXT_V,
89 KVM_RISCV_ISA_EXT_SVNAPOT,
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070090 KVM_RISCV_ISA_EXT_ZBA,
91 KVM_RISCV_ISA_EXT_ZBS,
92 KVM_RISCV_ISA_EXT_ZICNTR,
93 KVM_RISCV_ISA_EXT_ZICSR,
94 KVM_RISCV_ISA_EXT_ZIFENCEI,
95 KVM_RISCV_ISA_EXT_ZIHPM,
Elliott Hughes5e7f8f12022-10-01 15:10:58 +000096 KVM_RISCV_ISA_EXT_MAX,
97};
Christopher Ferris37c3f3c2023-07-10 10:59:05 -070098enum KVM_RISCV_SBI_EXT_ID {
99 KVM_RISCV_SBI_EXT_V01 = 0,
100 KVM_RISCV_SBI_EXT_TIME,
101 KVM_RISCV_SBI_EXT_IPI,
102 KVM_RISCV_SBI_EXT_RFENCE,
103 KVM_RISCV_SBI_EXT_SRST,
104 KVM_RISCV_SBI_EXT_HSM,
105 KVM_RISCV_SBI_EXT_PMU,
106 KVM_RISCV_SBI_EXT_EXPERIMENTAL,
107 KVM_RISCV_SBI_EXT_VENDOR,
108 KVM_RISCV_SBI_EXT_MAX,
109};
Elliott Hughes5e7f8f12022-10-01 15:10:58 +0000110#define KVM_RISCV_TIMER_STATE_OFF 0
111#define KVM_RISCV_TIMER_STATE_ON 1
112#define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
113#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
114#define KVM_REG_RISCV_TYPE_SHIFT 24
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700115#define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000
116#define KVM_REG_RISCV_SUBTYPE_SHIFT 16
Elliott Hughes5e7f8f12022-10-01 15:10:58 +0000117#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
118#define KVM_REG_RISCV_CONFIG_REG(name) (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
119#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
120#define KVM_REG_RISCV_CORE_REG(name) (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
121#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700122#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
123#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
Elliott Hughes5e7f8f12022-10-01 15:10:58 +0000124#define KVM_REG_RISCV_CSR_REG(name) (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700125#define KVM_REG_RISCV_CSR_AIA_REG(name) (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
Elliott Hughes5e7f8f12022-10-01 15:10:58 +0000126#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
127#define KVM_REG_RISCV_TIMER_REG(name) (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
128#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
129#define KVM_REG_RISCV_FP_F_REG(name) (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
130#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
131#define KVM_REG_RISCV_FP_D_REG(name) (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
132#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700133#define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
134#define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
135#define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
136#define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) ((__ext_id) / __BITS_PER_LONG)
137#define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) (1UL << ((__ext_id) % __BITS_PER_LONG))
138#define KVM_REG_RISCV_ISA_MULTI_REG_LAST KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700139#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
140#define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
141#define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
142#define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
143#define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) ((__ext_id) / __BITS_PER_LONG)
144#define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) (1UL << ((__ext_id) % __BITS_PER_LONG))
145#define KVM_REG_RISCV_SBI_MULTI_REG_LAST KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
Christopher Ferris8666d042023-09-06 14:55:31 -0700146#define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT)
147#define KVM_REG_RISCV_VECTOR_CSR_REG(name) (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
148#define KVM_REG_RISCV_VECTOR_REG(n) ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
149#define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
150#define KVM_DEV_RISCV_APLIC_SIZE 0x4000
151#define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000
152#define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000
153#define KVM_DEV_RISCV_IMSIC_SIZE 0x1000
154#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0
155#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0
156#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1
157#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2
158#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3
159#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4
160#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5
161#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6
162#define KVM_DEV_RISCV_AIA_MODE_EMUL 0
163#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1
164#define KVM_DEV_RISCV_AIA_MODE_AUTO 2
165#define KVM_DEV_RISCV_AIA_IDS_MIN 63
166#define KVM_DEV_RISCV_AIA_IDS_MAX 2048
167#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024
168#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8
169#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24
170#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56
171#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16
172#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8
173#define KVM_DEV_RISCV_AIA_GRP_ADDR 1
174#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0
175#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu))
176#define KVM_DEV_RISCV_AIA_ADDR_MAX (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
177#define KVM_DEV_RISCV_AIA_GRP_CTRL 2
178#define KVM_DEV_RISCV_AIA_CTRL_INIT 0
179#define KVM_DEV_RISCV_AIA_GRP_APLIC 3
180#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4
181#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12
182#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
183#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu,__isel) (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
184#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
185#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
186#define KVM_NR_IRQCHIPS 1
Elliott Hughes5e7f8f12022-10-01 15:10:58 +0000187#endif
188#endif