commit 67d1e5eb749124a14d6b5ecde63b2a4604830f3b
author Christopher Ferris <cferris@google.com> Tue Oct 31 13:36:37 2023 -0700
committer Christopher Ferris <cferris@google.com> Tue Oct 31 13:36:37 2023 -0700
tree f3df775a7ac267aa585b7ffcbbaea6853f976208
parent d0f5e4cf8aad28941695b0077266ed8bf1d9cc7c

Update to v6.6 kernel headers.

Kernel headers coming from:

Git: https://android.googlesource.com/kernel/common/
Branch: android-mainline
Tag: android-mainline-6.6

Test: Builds and bionic unit tests pass on raven.
Test: Able to log in to an Android GO 32 bit device.
Change-Id: Ib5ff5a23f382721d98d1e428a295c6794b190d8d

libc/kernel/uapi/asm-riscv/asm/kvm.h

diff --git a/libc/kernel/uapi/asm-riscv/asm/kvm.h b/libc/kernel/uapi/asm-riscv/asm/kvm.h
index c595872..c68cb7b 100644
--- a/libc/kernel/uapi/asm-riscv/asm/kvm.h
+++ b/libc/kernel/uapi/asm-riscv/asm/kvm.h
@@ -46,6 +46,7 @@
   unsigned long marchid;
   unsigned long mimpid;
   unsigned long zicboz_block_size;
+  unsigned long satp_mode;
 };
 struct kvm_riscv_core {
   struct user_regs_struct regs;
@@ -98,6 +99,12 @@
   KVM_RISCV_ISA_EXT_SSAIA,
   KVM_RISCV_ISA_EXT_V,
   KVM_RISCV_ISA_EXT_SVNAPOT,
+  KVM_RISCV_ISA_EXT_ZBA,
+  KVM_RISCV_ISA_EXT_ZBS,
+  KVM_RISCV_ISA_EXT_ZICNTR,
+  KVM_RISCV_ISA_EXT_ZICSR,
+  KVM_RISCV_ISA_EXT_ZIFENCEI,
+  KVM_RISCV_ISA_EXT_ZIHPM,
   KVM_RISCV_ISA_EXT_MAX,
 };
 enum KVM_RISCV_SBI_EXT_ID {
@@ -135,6 +142,12 @@
 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
 #define KVM_REG_RISCV_FP_D_REG(name) (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) ((__ext_id) / __BITS_PER_LONG)
+#define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) (1UL << ((__ext_id) % __BITS_PER_LONG))
+#define KVM_REG_RISCV_ISA_MULTI_REG_LAST KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)