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Christopher Ferris05d08e92016-02-04 13:16:38 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef VIRTGPU_DRM_H
20#define VIRTGPU_DRM_H
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -080025#define DRM_VIRTGPU_MAP 0x01
26#define DRM_VIRTGPU_EXECBUFFER 0x02
27#define DRM_VIRTGPU_GETPARAM 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
Christopher Ferris05d08e92016-02-04 13:16:38 -080029#define DRM_VIRTGPU_RESOURCE_INFO 0x05
30#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
31#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define DRM_VIRTGPU_WAIT 0x08
Christopher Ferris05d08e92016-02-04 13:16:38 -080033#define DRM_VIRTGPU_GET_CAPS 0x09
Christopher Ferris05667cd2021-02-16 16:01:34 -080034#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
Christopher Ferrisa4792612022-01-10 13:51:15 -080035#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
Christopher Ferrisd842e432019-03-07 10:21:59 -080036#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
37#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
Christopher Ferrisa4792612022-01-10 13:51:15 -080038#define VIRTGPU_EXECBUF_RING_IDX 0x04
39#define VIRTGPU_EXECBUF_FLAGS (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -080040struct drm_virtgpu_map {
Christopher Ferris106b3a82016-08-24 12:15:38 -070041 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070042 __u32 handle;
43 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -080044};
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070045#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
46#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS (VIRTGPU_EXECBUF_SYNCOBJ_RESET | 0)
47struct drm_virtgpu_execbuffer_syncobj {
48 __u32 handle;
49 __u32 flags;
50 __u64 point;
51};
Christopher Ferris05d08e92016-02-04 13:16:38 -080052struct drm_virtgpu_execbuffer {
Christopher Ferris106b3a82016-08-24 12:15:38 -070053 __u32 flags;
54 __u32 size;
55 __u64 command;
56 __u64 bo_handles;
Christopher Ferris106b3a82016-08-24 12:15:38 -070057 __u32 num_bo_handles;
Christopher Ferrisd842e432019-03-07 10:21:59 -080058 __s32 fence_fd;
Christopher Ferrisa4792612022-01-10 13:51:15 -080059 __u32 ring_idx;
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070060 __u32 syncobj_stride;
61 __u32 num_in_syncobjs;
62 __u32 num_out_syncobjs;
63 __u64 in_syncobjs;
64 __u64 out_syncobjs;
Christopher Ferris05d08e92016-02-04 13:16:38 -080065};
66#define VIRTGPU_PARAM_3D_FEATURES 1
Christopher Ferris76a1d452018-06-27 14:12:29 -070067#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2
Christopher Ferris05667cd2021-02-16 16:01:34 -080068#define VIRTGPU_PARAM_RESOURCE_BLOB 3
69#define VIRTGPU_PARAM_HOST_VISIBLE 4
70#define VIRTGPU_PARAM_CROSS_DEVICE 5
Christopher Ferrisa4792612022-01-10 13:51:15 -080071#define VIRTGPU_PARAM_CONTEXT_INIT 6
72#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7
Christopher Ferris05d08e92016-02-04 13:16:38 -080073struct drm_virtgpu_getparam {
Christopher Ferris106b3a82016-08-24 12:15:38 -070074 __u64 param;
75 __u64 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -080076};
77struct drm_virtgpu_resource_create {
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __u32 target;
79 __u32 format;
80 __u32 bind;
Christopher Ferris106b3a82016-08-24 12:15:38 -070081 __u32 width;
82 __u32 height;
83 __u32 depth;
84 __u32 array_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -070085 __u32 last_level;
86 __u32 nr_samples;
87 __u32 flags;
88 __u32 bo_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070089 __u32 res_handle;
90 __u32 size;
91 __u32 stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -080092};
93struct drm_virtgpu_resource_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -070094 __u32 bo_handle;
95 __u32 res_handle;
96 __u32 size;
Christopher Ferris05667cd2021-02-16 16:01:34 -080097 __u32 blob_mem;
Christopher Ferris05d08e92016-02-04 13:16:38 -080098};
99struct drm_virtgpu_3d_box {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700100 __u32 x;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700101 __u32 y;
102 __u32 z;
103 __u32 w;
104 __u32 h;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700105 __u32 d;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106};
107struct drm_virtgpu_3d_transfer_to_host {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700108 __u32 bo_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700109 struct drm_virtgpu_3d_box box;
110 __u32 level;
111 __u32 offset;
Christopher Ferris05667cd2021-02-16 16:01:34 -0800112 __u32 stride;
113 __u32 layer_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114};
115struct drm_virtgpu_3d_transfer_from_host {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700116 __u32 bo_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800117 struct drm_virtgpu_3d_box box;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118 __u32 level;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700119 __u32 offset;
Christopher Ferris05667cd2021-02-16 16:01:34 -0800120 __u32 stride;
121 __u32 layer_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800122};
123#define VIRTGPU_WAIT_NOWAIT 1
124struct drm_virtgpu_3d_wait {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700125 __u32 handle;
126 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800127};
128struct drm_virtgpu_get_caps {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700129 __u32 cap_set_id;
130 __u32 cap_set_ver;
131 __u64 addr;
132 __u32 size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700133 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134};
Christopher Ferris05667cd2021-02-16 16:01:34 -0800135struct drm_virtgpu_resource_create_blob {
136#define VIRTGPU_BLOB_MEM_GUEST 0x0001
137#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
138#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
139#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
140#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
141#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
142 __u32 blob_mem;
143 __u32 blob_flags;
144 __u32 bo_handle;
145 __u32 res_handle;
146 __u64 size;
147 __u32 pad;
148 __u32 cmd_size;
149 __u64 cmd;
150 __u64 blob_id;
151};
Christopher Ferrisa4792612022-01-10 13:51:15 -0800152#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
153#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
154#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
155struct drm_virtgpu_context_set_param {
156 __u64 param;
157 __u64 value;
158};
159struct drm_virtgpu_context_init {
160 __u32 num_params;
161 __u32 pad;
162 __u64 ctx_set_params;
163};
164#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800165#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
Christopher Ferrisd842e432019-03-07 10:21:59 -0800166#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700167#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800168#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
169#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
170#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700171#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800172#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
173#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
Christopher Ferris05667cd2021-02-16 16:01:34 -0800174#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)
Christopher Ferrisa4792612022-01-10 13:51:15 -0800175#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700176#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800177}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700178#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800179#endif