Elliott Hughes | 180edef | 2023-11-02 00:08:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is auto-generated. Modifications will be lost. |
| 3 | * |
| 4 | * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ |
| 5 | * for more information. |
| 6 | */ |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 7 | #ifndef _UAPI__LINUX_MII_H__ |
| 8 | #define _UAPI__LINUX_MII_H__ |
| 9 | #include <linux/types.h> |
| 10 | #include <linux/ethtool.h> |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 11 | #define MII_BMCR 0x00 |
| 12 | #define MII_BMSR 0x01 |
| 13 | #define MII_PHYSID1 0x02 |
| 14 | #define MII_PHYSID2 0x03 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 15 | #define MII_ADVERTISE 0x04 |
| 16 | #define MII_LPA 0x05 |
| 17 | #define MII_EXPANSION 0x06 |
| 18 | #define MII_CTRL1000 0x09 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 19 | #define MII_STAT1000 0x0a |
| 20 | #define MII_MMD_CTRL 0x0d |
| 21 | #define MII_MMD_DATA 0x0e |
| 22 | #define MII_ESTATUS 0x0f |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 23 | #define MII_DCOUNTER 0x12 |
| 24 | #define MII_FCSCOUNTER 0x13 |
| 25 | #define MII_NWAYTEST 0x14 |
| 26 | #define MII_RERRCOUNTER 0x15 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 27 | #define MII_SREVISION 0x16 |
| 28 | #define MII_RESV1 0x17 |
| 29 | #define MII_LBRERROR 0x18 |
| 30 | #define MII_PHYADDR 0x19 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 31 | #define MII_RESV2 0x1a |
| 32 | #define MII_TPISTATUS 0x1b |
| 33 | #define MII_NCONFIG 0x1c |
| 34 | #define BMCR_RESV 0x003f |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 35 | #define BMCR_SPEED1000 0x0040 |
| 36 | #define BMCR_CTST 0x0080 |
| 37 | #define BMCR_FULLDPLX 0x0100 |
| 38 | #define BMCR_ANRESTART 0x0200 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 39 | #define BMCR_ISOLATE 0x0400 |
| 40 | #define BMCR_PDOWN 0x0800 |
| 41 | #define BMCR_ANENABLE 0x1000 |
| 42 | #define BMCR_SPEED100 0x2000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 43 | #define BMCR_LOOPBACK 0x4000 |
| 44 | #define BMCR_RESET 0x8000 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 45 | #define BMCR_SPEED10 0x0000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 46 | #define BMSR_ERCAP 0x0001 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 47 | #define BMSR_JCD 0x0002 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 48 | #define BMSR_LSTATUS 0x0004 |
| 49 | #define BMSR_ANEGCAPABLE 0x0008 |
| 50 | #define BMSR_RFAULT 0x0010 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 51 | #define BMSR_ANEGCOMPLETE 0x0020 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 52 | #define BMSR_RESV 0x00c0 |
| 53 | #define BMSR_ESTATEN 0x0100 |
| 54 | #define BMSR_100HALF2 0x0200 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 55 | #define BMSR_100FULL2 0x0400 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 56 | #define BMSR_10HALF 0x0800 |
| 57 | #define BMSR_10FULL 0x1000 |
| 58 | #define BMSR_100HALF 0x2000 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 59 | #define BMSR_100FULL 0x4000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 60 | #define BMSR_100BASE4 0x8000 |
| 61 | #define ADVERTISE_SLCT 0x001f |
| 62 | #define ADVERTISE_CSMA 0x0001 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 63 | #define ADVERTISE_10HALF 0x0020 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 64 | #define ADVERTISE_1000XFULL 0x0020 |
| 65 | #define ADVERTISE_10FULL 0x0040 |
| 66 | #define ADVERTISE_1000XHALF 0x0040 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 67 | #define ADVERTISE_100HALF 0x0080 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 68 | #define ADVERTISE_1000XPAUSE 0x0080 |
| 69 | #define ADVERTISE_100FULL 0x0100 |
| 70 | #define ADVERTISE_1000XPSE_ASYM 0x0100 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 71 | #define ADVERTISE_100BASE4 0x0200 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 72 | #define ADVERTISE_PAUSE_CAP 0x0400 |
| 73 | #define ADVERTISE_PAUSE_ASYM 0x0800 |
| 74 | #define ADVERTISE_RESV 0x1000 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 75 | #define ADVERTISE_RFAULT 0x2000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 76 | #define ADVERTISE_LPACK 0x4000 |
| 77 | #define ADVERTISE_NPAGE 0x8000 |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 78 | #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 79 | #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 80 | #define LPA_SLCT 0x001f |
| 81 | #define LPA_10HALF 0x0020 |
| 82 | #define LPA_1000XFULL 0x0020 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 83 | #define LPA_10FULL 0x0040 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 84 | #define LPA_1000XHALF 0x0040 |
| 85 | #define LPA_100HALF 0x0080 |
| 86 | #define LPA_1000XPAUSE 0x0080 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 87 | #define LPA_100FULL 0x0100 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 88 | #define LPA_1000XPAUSE_ASYM 0x0100 |
| 89 | #define LPA_100BASE4 0x0200 |
| 90 | #define LPA_PAUSE_CAP 0x0400 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 91 | #define LPA_PAUSE_ASYM 0x0800 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 92 | #define LPA_RESV 0x1000 |
| 93 | #define LPA_RFAULT 0x2000 |
| 94 | #define LPA_LPACK 0x4000 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 95 | #define LPA_NPAGE 0x8000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 96 | #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) |
| 97 | #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) |
| 98 | #define EXPANSION_NWAY 0x0001 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 99 | #define EXPANSION_LCWP 0x0002 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 100 | #define EXPANSION_ENABLENPAGE 0x0004 |
| 101 | #define EXPANSION_NPCAPABLE 0x0008 |
| 102 | #define EXPANSION_MFAULTS 0x0010 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 103 | #define EXPANSION_RESV 0xffe0 |
Christopher Ferris | b8a95e2 | 2019-10-02 18:29:20 -0700 | [diff] [blame] | 104 | #define ESTATUS_1000_XFULL 0x8000 |
| 105 | #define ESTATUS_1000_XHALF 0x4000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 106 | #define ESTATUS_1000_TFULL 0x2000 |
| 107 | #define ESTATUS_1000_THALF 0x1000 |
| 108 | #define NWAYTEST_RESV1 0x00ff |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 109 | #define NWAYTEST_LOOPBACK 0x0100 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 110 | #define NWAYTEST_RESV2 0xfe00 |
Christopher Ferris | bb9fcb4 | 2020-04-06 11:38:04 -0700 | [diff] [blame] | 111 | #define ADVERTISE_SGMII 0x0001 |
| 112 | #define LPA_SGMII 0x0001 |
Christopher Ferris | af09c70 | 2020-06-01 20:29:29 -0700 | [diff] [blame] | 113 | #define LPA_SGMII_SPD_MASK 0x0c00 |
| 114 | #define LPA_SGMII_FULL_DUPLEX 0x1000 |
Christopher Ferris | bb9fcb4 | 2020-04-06 11:38:04 -0700 | [diff] [blame] | 115 | #define LPA_SGMII_DPX_SPD_MASK 0x1C00 |
Christopher Ferris | af09c70 | 2020-06-01 20:29:29 -0700 | [diff] [blame] | 116 | #define LPA_SGMII_10 0x0000 |
Christopher Ferris | bb9fcb4 | 2020-04-06 11:38:04 -0700 | [diff] [blame] | 117 | #define LPA_SGMII_10HALF 0x0000 |
| 118 | #define LPA_SGMII_10FULL 0x1000 |
Christopher Ferris | af09c70 | 2020-06-01 20:29:29 -0700 | [diff] [blame] | 119 | #define LPA_SGMII_100 0x0400 |
Christopher Ferris | bb9fcb4 | 2020-04-06 11:38:04 -0700 | [diff] [blame] | 120 | #define LPA_SGMII_100HALF 0x0400 |
| 121 | #define LPA_SGMII_100FULL 0x1400 |
Christopher Ferris | af09c70 | 2020-06-01 20:29:29 -0700 | [diff] [blame] | 122 | #define LPA_SGMII_1000 0x0800 |
Christopher Ferris | bb9fcb4 | 2020-04-06 11:38:04 -0700 | [diff] [blame] | 123 | #define LPA_SGMII_1000HALF 0x0800 |
| 124 | #define LPA_SGMII_1000FULL 0x1800 |
| 125 | #define LPA_SGMII_LINK 0x8000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 126 | #define ADVERTISE_1000FULL 0x0200 |
| 127 | #define ADVERTISE_1000HALF 0x0100 |
Christopher Ferris | 8177cdf | 2020-08-03 11:53:55 -0700 | [diff] [blame] | 128 | #define CTL1000_PREFER_MASTER 0x0400 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 129 | #define CTL1000_AS_MASTER 0x0800 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 130 | #define CTL1000_ENABLE_MASTER 0x1000 |
Christopher Ferris | 9ce2884 | 2018-10-25 12:11:39 -0700 | [diff] [blame] | 131 | #define LPA_1000MSFAIL 0x8000 |
Christopher Ferris | 8177cdf | 2020-08-03 11:53:55 -0700 | [diff] [blame] | 132 | #define LPA_1000MSRES 0x4000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 133 | #define LPA_1000LOCALRXOK 0x2000 |
| 134 | #define LPA_1000REMRXOK 0x1000 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 135 | #define LPA_1000FULL 0x0800 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 136 | #define LPA_1000HALF 0x0400 |
| 137 | #define FLOW_CTRL_TX 0x01 |
| 138 | #define FLOW_CTRL_RX 0x02 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 139 | #define MII_MMD_CTRL_DEVAD_MASK 0x1f |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 140 | #define MII_MMD_CTRL_ADDR 0x0000 |
| 141 | #define MII_MMD_CTRL_NOINCR 0x4000 |
| 142 | #define MII_MMD_CTRL_INCR_RDWT 0x8000 |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 143 | #define MII_MMD_CTRL_INCR_ON_WT 0xC000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 144 | struct mii_ioctl_data { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 145 | __u16 phy_id; |
| 146 | __u16 reg_num; |
Christopher Ferris | 6a9755d | 2017-01-13 14:09:31 -0800 | [diff] [blame] | 147 | __u16 val_in; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 148 | __u16 val_out; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 149 | }; |
| 150 | #endif |