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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__LINUX_MII_H__
20#define _UAPI__LINUX_MII_H__
21#include <linux/types.h>
22#include <linux/ethtool.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070023#define MII_BMCR 0x00
24#define MII_BMSR 0x01
25#define MII_PHYSID1 0x02
26#define MII_PHYSID2 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define MII_ADVERTISE 0x04
28#define MII_LPA 0x05
29#define MII_EXPANSION 0x06
30#define MII_CTRL1000 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define MII_STAT1000 0x0a
32#define MII_MMD_CTRL 0x0d
33#define MII_MMD_DATA 0x0e
34#define MII_ESTATUS 0x0f
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define MII_DCOUNTER 0x12
36#define MII_FCSCOUNTER 0x13
37#define MII_NWAYTEST 0x14
38#define MII_RERRCOUNTER 0x15
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define MII_SREVISION 0x16
40#define MII_RESV1 0x17
41#define MII_LBRERROR 0x18
42#define MII_PHYADDR 0x19
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define MII_RESV2 0x1a
44#define MII_TPISTATUS 0x1b
45#define MII_NCONFIG 0x1c
46#define BMCR_RESV 0x003f
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define BMCR_SPEED1000 0x0040
48#define BMCR_CTST 0x0080
49#define BMCR_FULLDPLX 0x0100
50#define BMCR_ANRESTART 0x0200
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define BMCR_ISOLATE 0x0400
52#define BMCR_PDOWN 0x0800
53#define BMCR_ANENABLE 0x1000
54#define BMCR_SPEED100 0x2000
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define BMCR_LOOPBACK 0x4000
56#define BMCR_RESET 0x8000
Christopher Ferris6a9755d2017-01-13 14:09:31 -080057#define BMCR_SPEED10 0x0000
Ben Cheng655a7c02013-10-16 16:09:24 -070058#define BMSR_ERCAP 0x0001
Christopher Ferris6a9755d2017-01-13 14:09:31 -080059#define BMSR_JCD 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -070060#define BMSR_LSTATUS 0x0004
61#define BMSR_ANEGCAPABLE 0x0008
62#define BMSR_RFAULT 0x0010
Christopher Ferris6a9755d2017-01-13 14:09:31 -080063#define BMSR_ANEGCOMPLETE 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -070064#define BMSR_RESV 0x00c0
65#define BMSR_ESTATEN 0x0100
66#define BMSR_100HALF2 0x0200
Christopher Ferris6a9755d2017-01-13 14:09:31 -080067#define BMSR_100FULL2 0x0400
Ben Cheng655a7c02013-10-16 16:09:24 -070068#define BMSR_10HALF 0x0800
69#define BMSR_10FULL 0x1000
70#define BMSR_100HALF 0x2000
Christopher Ferris6a9755d2017-01-13 14:09:31 -080071#define BMSR_100FULL 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -070072#define BMSR_100BASE4 0x8000
73#define ADVERTISE_SLCT 0x001f
74#define ADVERTISE_CSMA 0x0001
Christopher Ferris6a9755d2017-01-13 14:09:31 -080075#define ADVERTISE_10HALF 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -070076#define ADVERTISE_1000XFULL 0x0020
77#define ADVERTISE_10FULL 0x0040
78#define ADVERTISE_1000XHALF 0x0040
Christopher Ferris6a9755d2017-01-13 14:09:31 -080079#define ADVERTISE_100HALF 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -070080#define ADVERTISE_1000XPAUSE 0x0080
81#define ADVERTISE_100FULL 0x0100
82#define ADVERTISE_1000XPSE_ASYM 0x0100
Christopher Ferris6a9755d2017-01-13 14:09:31 -080083#define ADVERTISE_100BASE4 0x0200
Ben Cheng655a7c02013-10-16 16:09:24 -070084#define ADVERTISE_PAUSE_CAP 0x0400
85#define ADVERTISE_PAUSE_ASYM 0x0800
86#define ADVERTISE_RESV 0x1000
Christopher Ferris6a9755d2017-01-13 14:09:31 -080087#define ADVERTISE_RFAULT 0x2000
Ben Cheng655a7c02013-10-16 16:09:24 -070088#define ADVERTISE_LPACK 0x4000
89#define ADVERTISE_NPAGE 0x8000
Tao Baod7db5942015-01-28 10:07:51 -080090#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
Christopher Ferris6a9755d2017-01-13 14:09:31 -080091#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL)
Ben Cheng655a7c02013-10-16 16:09:24 -070092#define LPA_SLCT 0x001f
93#define LPA_10HALF 0x0020
94#define LPA_1000XFULL 0x0020
Christopher Ferris6a9755d2017-01-13 14:09:31 -080095#define LPA_10FULL 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -070096#define LPA_1000XHALF 0x0040
97#define LPA_100HALF 0x0080
98#define LPA_1000XPAUSE 0x0080
Christopher Ferris6a9755d2017-01-13 14:09:31 -080099#define LPA_100FULL 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700100#define LPA_1000XPAUSE_ASYM 0x0100
101#define LPA_100BASE4 0x0200
102#define LPA_PAUSE_CAP 0x0400
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800103#define LPA_PAUSE_ASYM 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700104#define LPA_RESV 0x1000
105#define LPA_RFAULT 0x2000
106#define LPA_LPACK 0x4000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800107#define LPA_NPAGE 0x8000
Ben Cheng655a7c02013-10-16 16:09:24 -0700108#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
109#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
110#define EXPANSION_NWAY 0x0001
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800111#define EXPANSION_LCWP 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700112#define EXPANSION_ENABLENPAGE 0x0004
113#define EXPANSION_NPCAPABLE 0x0008
114#define EXPANSION_MFAULTS 0x0010
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800115#define EXPANSION_RESV 0xffe0
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700116#define ESTATUS_1000_XFULL 0x8000
117#define ESTATUS_1000_XHALF 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700118#define ESTATUS_1000_TFULL 0x2000
119#define ESTATUS_1000_THALF 0x1000
120#define NWAYTEST_RESV1 0x00ff
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800121#define NWAYTEST_LOOPBACK 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700122#define NWAYTEST_RESV2 0xfe00
123#define ADVERTISE_1000FULL 0x0200
124#define ADVERTISE_1000HALF 0x0100
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800125#define CTL1000_AS_MASTER 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700126#define CTL1000_ENABLE_MASTER 0x1000
Christopher Ferris9ce28842018-10-25 12:11:39 -0700127#define LPA_1000MSFAIL 0x8000
Ben Cheng655a7c02013-10-16 16:09:24 -0700128#define LPA_1000LOCALRXOK 0x2000
129#define LPA_1000REMRXOK 0x1000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800130#define LPA_1000FULL 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700131#define LPA_1000HALF 0x0400
132#define FLOW_CTRL_TX 0x01
133#define FLOW_CTRL_RX 0x02
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800134#define MII_MMD_CTRL_DEVAD_MASK 0x1f
Ben Cheng655a7c02013-10-16 16:09:24 -0700135#define MII_MMD_CTRL_ADDR 0x0000
136#define MII_MMD_CTRL_NOINCR 0x4000
137#define MII_MMD_CTRL_INCR_RDWT 0x8000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800138#define MII_MMD_CTRL_INCR_ON_WT 0xC000
Ben Cheng655a7c02013-10-16 16:09:24 -0700139struct mii_ioctl_data {
Tao Baod7db5942015-01-28 10:07:51 -0800140 __u16 phy_id;
141 __u16 reg_num;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800142 __u16 val_in;
Tao Baod7db5942015-01-28 10:07:51 -0800143 __u16 val_out;
Ben Cheng655a7c02013-10-16 16:09:24 -0700144};
145#endif