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gerrit.omnirom.org / android_bionic / 0b1a2826508ee5b191650d1d8b1f6b028e970f3b / . / libc / kernel / uapi / drm / tegra_drm.h
blob: e5d8b6763d7b48fd4690a3f865c92c96a005a974 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]21#include <drm/drm.h>
22#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25struct drm_tegra_gem_create {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]26 __u64 size;
27 __u32 flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]29 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31struct drm_tegra_gem_mmap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]32 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]34 __u32 pad;
35 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]37struct drm_tegra_syncpt_read {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]39 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]40 __u32 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]42struct drm_tegra_syncpt_incr {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]44 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]45 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47struct drm_tegra_syncpt_wait {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]49 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]50 __u32 thresh;
51 __u32 timeout;
52 __u32 value;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]54};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]55#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
56struct drm_tegra_open_channel {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]57 __u32 client;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]59 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]60 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]61};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]62struct drm_tegra_close_channel {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]64 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65};
66struct drm_tegra_get_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]67 __u64 context;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]69 __u32 index;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]70 __u32 id;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]71};
72struct drm_tegra_get_syncpt_base {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]74 __u64 context;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]75 __u32 syncpt;
76 __u32 id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]77};
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]79struct drm_tegra_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]80 __u32 id;
81 __u32 incrs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82};
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]84struct drm_tegra_cmdbuf {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]85 __u32 handle;
86 __u32 offset;
87 __u32 words;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]89 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90};
91struct drm_tegra_reloc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]92 struct {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]94 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]95 __u32 offset;
96 } cmdbuf;
97 struct {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]99 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]100 __u32 offset;
101 } target;
102 __u32 shift;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]104 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]105};
106struct drm_tegra_waitchk {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]107 __u32 handle;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]109 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 __u32 syncpt;
111 __u32 thresh;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]112};
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]114struct drm_tegra_submit {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]115 __u64 context;
116 __u32 num_syncpts;
117 __u32 num_cmdbufs;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]119 __u32 num_relocs;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]120 __u32 num_waitchks;
121 __u32 waitchk_mask;
122 __u32 timeout;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]124 __u64 syncpts;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]125 __u64 cmdbufs;
126 __u64 relocs;
127 __u64 waitchks;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]129 __u32 fence;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]130 __u32 reserved[5];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]132#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]134#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]135#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
136struct drm_tegra_gem_set_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]137 __u32 handle;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]139 __u32 mode;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]140 __u32 value;
141 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]142};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]144struct drm_tegra_gem_get_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]145 __u32 handle;
146 __u32 mode;
147 __u32 value;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]149 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]150};
151#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
152#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]154struct drm_tegra_gem_set_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 __u32 handle;
156 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]157};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]159struct drm_tegra_gem_get_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]160 __u32 handle;
161 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]162};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]164#define DRM_TEGRA_GEM_CREATE 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]165#define DRM_TEGRA_GEM_MMAP 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]166#define DRM_TEGRA_SYNCPT_READ 0x02
167#define DRM_TEGRA_SYNCPT_INCR 0x03
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]169#define DRM_TEGRA_SYNCPT_WAIT 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]170#define DRM_TEGRA_OPEN_CHANNEL 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]171#define DRM_TEGRA_CLOSE_CHANNEL 0x06
172#define DRM_TEGRA_GET_SYNCPT 0x07
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]174#define DRM_TEGRA_SUBMIT 0x08
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]175#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
176#define DRM_TEGRA_GEM_SET_TILING 0x0a
177#define DRM_TEGRA_GEM_GET_TILING 0x0b
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]179#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]180#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
182#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]184#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]185#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]186#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
187#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]189#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]190#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]191#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]192#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]194#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]195#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
196#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
197#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]199#endif