Andrew Walbran | 730375d | 2022-12-21 14:04:34 +0000 | [diff] [blame] | 1 | // Copyright 2022, The Android Open Source Project |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | |
| 15 | //! Library for working with (VirtIO) PCI devices discovered from a device tree. |
| 16 | |
| 17 | #![no_std] |
| 18 | |
| 19 | use core::{ |
| 20 | ffi::CStr, |
| 21 | fmt::{self, Display, Formatter}, |
| 22 | ops::Range, |
| 23 | }; |
| 24 | use libfdt::{AddressRange, Fdt, FdtError, FdtNode}; |
| 25 | use log::debug; |
Andrew Walbran | 336d0cb | 2023-01-06 16:33:15 +0000 | [diff] [blame] | 26 | use virtio_drivers::transport::pci::bus::{Cam, PciRoot}; |
Andrew Walbran | 730375d | 2022-12-21 14:04:34 +0000 | [diff] [blame] | 27 | |
| 28 | /// PCI MMIO configuration region size. |
| 29 | const PCI_CFG_SIZE: usize = 0x100_0000; |
| 30 | |
| 31 | /// An error parsing a PCI node from an FDT. |
| 32 | #[derive(Clone, Debug, Eq, PartialEq)] |
| 33 | pub enum PciError { |
| 34 | /// Error getting PCI node from FDT. |
| 35 | FdtErrorPci(FdtError), |
| 36 | /// Failed to find PCI bus in FDT. |
| 37 | FdtNoPci, |
| 38 | /// Error getting `reg` property from PCI node. |
| 39 | FdtErrorReg(FdtError), |
| 40 | /// PCI node missing `reg` property. |
| 41 | FdtMissingReg, |
| 42 | /// Empty `reg property on PCI node. |
| 43 | FdtRegEmpty, |
| 44 | /// PCI `reg` property missing size. |
| 45 | FdtRegMissingSize, |
| 46 | /// PCI CAM size reported by FDT is not what we expected. |
| 47 | CamWrongSize(usize), |
| 48 | /// Error getting `ranges` property from PCI node. |
| 49 | FdtErrorRanges(FdtError), |
| 50 | /// PCI node missing `ranges` property. |
| 51 | FdtMissingRanges, |
| 52 | /// Bus address is not equal to CPU physical address in `ranges` property. |
| 53 | RangeAddressMismatch { |
| 54 | /// A bus address from the `ranges` property. |
| 55 | bus_address: u64, |
| 56 | /// The corresponding CPU physical address from the `ranges` property. |
| 57 | cpu_physical: u64, |
| 58 | }, |
| 59 | /// No suitable PCI memory range found. |
| 60 | NoSuitableRange, |
| 61 | } |
| 62 | |
| 63 | impl Display for PciError { |
| 64 | fn fmt(&self, f: &mut Formatter) -> fmt::Result { |
| 65 | match self { |
| 66 | Self::FdtErrorPci(e) => write!(f, "Error getting PCI node from FDT: {}", e), |
| 67 | Self::FdtNoPci => write!(f, "Failed to find PCI bus in FDT."), |
| 68 | Self::FdtErrorReg(e) => write!(f, "Error getting reg property from PCI node: {}", e), |
| 69 | Self::FdtMissingReg => write!(f, "PCI node missing reg property."), |
| 70 | Self::FdtRegEmpty => write!(f, "Empty reg property on PCI node."), |
| 71 | Self::FdtRegMissingSize => write!(f, "PCI reg property missing size."), |
| 72 | Self::CamWrongSize(cam_size) => write!( |
| 73 | f, |
| 74 | "FDT says PCI CAM is {} bytes but we expected {}.", |
| 75 | cam_size, PCI_CFG_SIZE |
| 76 | ), |
| 77 | Self::FdtErrorRanges(e) => { |
| 78 | write!(f, "Error getting ranges property from PCI node: {}", e) |
| 79 | } |
| 80 | Self::FdtMissingRanges => write!(f, "PCI node missing ranges property."), |
| 81 | Self::RangeAddressMismatch { bus_address, cpu_physical } => { |
| 82 | write!( |
| 83 | f, |
| 84 | "bus address {:#018x} != CPU physical address {:#018x}", |
| 85 | bus_address, cpu_physical |
| 86 | ) |
| 87 | } |
| 88 | Self::NoSuitableRange => write!(f, "No suitable PCI memory range found."), |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | /// Information about the PCI bus parsed from the device tree. |
Andrew Walbran | b398fc8 | 2023-01-24 14:45:46 +0000 | [diff] [blame] | 94 | #[derive(Clone, Debug)] |
Andrew Walbran | 730375d | 2022-12-21 14:04:34 +0000 | [diff] [blame] | 95 | pub struct PciInfo { |
| 96 | /// The MMIO range used by the memory-mapped PCI CAM. |
| 97 | pub cam_range: Range<usize>, |
| 98 | /// The MMIO range from which 32-bit PCI BARs should be allocated. |
| 99 | pub bar_range: Range<u32>, |
| 100 | } |
| 101 | |
| 102 | impl PciInfo { |
| 103 | /// Finds the PCI node in the FDT, parses its properties and validates it. |
| 104 | pub fn from_fdt(fdt: &Fdt) -> Result<Self, PciError> { |
| 105 | let pci_node = pci_node(fdt)?; |
| 106 | |
| 107 | let cam_range = parse_cam_range(&pci_node)?; |
| 108 | let bar_range = parse_ranges(&pci_node)?; |
| 109 | |
| 110 | Ok(Self { cam_range, bar_range }) |
| 111 | } |
| 112 | |
| 113 | /// Returns the `PciRoot` for the memory-mapped CAM found in the FDT. The CAM should be mapped |
| 114 | /// before this is called, by calling [`PciInfo::map`]. |
| 115 | /// |
| 116 | /// # Safety |
| 117 | /// |
| 118 | /// To prevent concurrent access, only one `PciRoot` should exist in the program. Thus this |
| 119 | /// method must only be called once, and there must be no other `PciRoot` constructed using the |
| 120 | /// same CAM. |
| 121 | pub unsafe fn make_pci_root(&self) -> PciRoot { |
| 122 | PciRoot::new(self.cam_range.start as *mut u8, Cam::MmioCam) |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | /// Finds an FDT node with compatible=pci-host-cam-generic. |
| 127 | fn pci_node(fdt: &Fdt) -> Result<FdtNode, PciError> { |
| 128 | fdt.compatible_nodes(CStr::from_bytes_with_nul(b"pci-host-cam-generic\0").unwrap()) |
| 129 | .map_err(PciError::FdtErrorPci)? |
| 130 | .next() |
| 131 | .ok_or(PciError::FdtNoPci) |
| 132 | } |
| 133 | |
| 134 | /// Parses the "reg" property of the given PCI FDT node to find the MMIO CAM range. |
| 135 | fn parse_cam_range(pci_node: &FdtNode) -> Result<Range<usize>, PciError> { |
| 136 | let pci_reg = pci_node |
| 137 | .reg() |
| 138 | .map_err(PciError::FdtErrorReg)? |
| 139 | .ok_or(PciError::FdtMissingReg)? |
| 140 | .next() |
| 141 | .ok_or(PciError::FdtRegEmpty)?; |
| 142 | let cam_addr = pci_reg.addr as usize; |
| 143 | let cam_size = pci_reg.size.ok_or(PciError::FdtRegMissingSize)? as usize; |
| 144 | debug!("Found PCI CAM at {:#x}-{:#x}", cam_addr, cam_addr + cam_size); |
| 145 | // Check that the CAM is the size we expect, so we don't later try accessing it beyond its |
| 146 | // bounds. If it is a different size then something is very wrong and we shouldn't continue to |
| 147 | // access it; maybe there is some new version of PCI we don't know about. |
| 148 | if cam_size != PCI_CFG_SIZE { |
| 149 | return Err(PciError::CamWrongSize(cam_size)); |
| 150 | } |
| 151 | |
| 152 | Ok(cam_addr..cam_addr + cam_size) |
| 153 | } |
| 154 | |
| 155 | /// Parses the "ranges" property of the given PCI FDT node, and returns the largest suitable range |
| 156 | /// to use for non-prefetchable 32-bit memory BARs. |
| 157 | fn parse_ranges(pci_node: &FdtNode) -> Result<Range<u32>, PciError> { |
| 158 | let mut memory_address = 0; |
| 159 | let mut memory_size = 0; |
| 160 | |
| 161 | for AddressRange { addr: (flags, bus_address), parent_addr: cpu_physical, size } in pci_node |
| 162 | .ranges::<(u32, u64), u64, u64>() |
| 163 | .map_err(PciError::FdtErrorRanges)? |
| 164 | .ok_or(PciError::FdtMissingRanges)? |
| 165 | { |
| 166 | let flags = PciMemoryFlags(flags); |
| 167 | let prefetchable = flags.prefetchable(); |
| 168 | let range_type = flags.range_type(); |
| 169 | debug!( |
| 170 | "range: {:?} {}prefetchable bus address: {:#018x} CPU physical address: {:#018x} size: {:#018x}", |
| 171 | range_type, |
| 172 | if prefetchable { "" } else { "non-" }, |
| 173 | bus_address, |
| 174 | cpu_physical, |
| 175 | size, |
| 176 | ); |
| 177 | |
| 178 | // Use a 64-bit range for 32-bit memory, if it is low enough, because crosvm doesn't |
| 179 | // currently provide any 32-bit ranges. |
| 180 | if !prefetchable |
| 181 | && matches!(range_type, PciRangeType::Memory32 | PciRangeType::Memory64) |
| 182 | && size > memory_size.into() |
| 183 | && bus_address + size < u32::MAX.into() |
| 184 | { |
| 185 | if bus_address != cpu_physical { |
| 186 | return Err(PciError::RangeAddressMismatch { bus_address, cpu_physical }); |
| 187 | } |
| 188 | memory_address = u32::try_from(cpu_physical).unwrap(); |
| 189 | memory_size = u32::try_from(size).unwrap(); |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | if memory_size == 0 { |
| 194 | return Err(PciError::NoSuitableRange); |
| 195 | } |
| 196 | |
| 197 | Ok(memory_address..memory_address + memory_size) |
| 198 | } |
| 199 | |
| 200 | #[derive(Copy, Clone, Debug, Eq, PartialEq)] |
| 201 | struct PciMemoryFlags(u32); |
| 202 | |
| 203 | impl PciMemoryFlags { |
| 204 | pub fn prefetchable(self) -> bool { |
| 205 | self.0 & 0x80000000 != 0 |
| 206 | } |
| 207 | |
| 208 | pub fn range_type(self) -> PciRangeType { |
| 209 | PciRangeType::from((self.0 & 0x3000000) >> 24) |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | #[derive(Copy, Clone, Debug, Eq, PartialEq)] |
| 214 | enum PciRangeType { |
| 215 | ConfigurationSpace, |
| 216 | IoSpace, |
| 217 | Memory32, |
| 218 | Memory64, |
| 219 | } |
| 220 | |
| 221 | impl From<u32> for PciRangeType { |
| 222 | fn from(value: u32) -> Self { |
| 223 | match value { |
| 224 | 0 => Self::ConfigurationSpace, |
| 225 | 1 => Self::IoSpace, |
| 226 | 2 => Self::Memory32, |
| 227 | 3 => Self::Memory64, |
| 228 | _ => panic!("Tried to convert invalid range type {}", value), |
| 229 | } |
| 230 | } |
| 231 | } |