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Jiyong Park196115b2023-02-25 02:01:15 +09001/*
2 * Copyright (C) 2022 Google LLC
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6
7#define PLACEHOLDER 0xffffffff
8#define PLACEHOLDER2 PLACEHOLDER PLACEHOLDER
9#define PLACEHOLDER4 PLACEHOLDER2 PLACEHOLDER2
10
Jiyong Parka503f422023-03-21 19:27:04 +090011#define IRQ_BASE 4
12
Jiyong Park196115b2023-02-25 02:01:15 +090013/dts-v1/;
14
15/ {
16 interrupt-parent = <&intc>;
17 compatible = "linux,dummy-virt";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen {
22 stdout-path = "/uart@3f8";
23 linux,pci-probe-only = <1>;
24 kaslr-seed = <PLACEHOLDER2>;
25 avf,strict-boot;
26 avf,new-instance;
27 };
28
29 memory {
30 device_type = "memory";
Jiyong Parkef85e832023-02-25 02:03:39 +090031 reg = <0x00 0x80000000 PLACEHOLDER2>;
Jiyong Park196115b2023-02-25 02:01:15 +090032 };
33
34 reserved-memory {
35 #address-cells = <2>;
36 #size-cells = <2>;
37 ranges;
38 swiotlb: restricted_dma_reserved {
39 compatible = "restricted-dma-pool";
Pierre-Clément Tosic27c4272023-05-19 15:46:26 +000040 reg = <PLACEHOLDER4>;
Jiyong Park196115b2023-02-25 02:01:15 +090041 size = <PLACEHOLDER2>;
42 alignment = <PLACEHOLDER2>;
43 };
44
45 dice {
46 compatible = "google,open-dice";
47 no-map;
48 reg = <PLACEHOLDER4>;
49 };
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 cpu@0 {
56 device_type = "cpu";
57 compatible = "arm,arm-v8";
58 enable-method = "psci";
59 reg = <0>;
60 };
61 cpu@1 {
62 device_type = "cpu";
63 compatible = "arm,arm-v8";
64 enable-method = "psci";
65 reg = <1>;
66 };
67 cpu@2 {
68 device_type = "cpu";
69 compatible = "arm,arm-v8";
70 enable-method = "psci";
71 reg = <2>;
72 };
73 cpu@3 {
74 device_type = "cpu";
75 compatible = "arm,arm-v8";
76 enable-method = "psci";
77 reg = <3>;
78 };
79 cpu@4 {
80 device_type = "cpu";
81 compatible = "arm,arm-v8";
82 enable-method = "psci";
83 reg = <4>;
84 };
85 cpu@5 {
86 device_type = "cpu";
87 compatible = "arm,arm-v8";
88 enable-method = "psci";
89 reg = <5>;
90 };
91 cpu@6 {
92 device_type = "cpu";
93 compatible = "arm,arm-v8";
94 enable-method = "psci";
95 reg = <6>;
96 };
97 cpu@7 {
98 device_type = "cpu";
99 compatible = "arm,arm-v8";
100 enable-method = "psci";
101 reg = <7>;
102 };
103 cpu@8 {
104 device_type = "cpu";
105 compatible = "arm,arm-v8";
106 enable-method = "psci";
107 reg = <8>;
108 };
109 cpu@9 {
110 device_type = "cpu";
111 compatible = "arm,arm-v8";
112 enable-method = "psci";
113 reg = <9>;
114 };
115 cpu@10 {
116 device_type = "cpu";
117 compatible = "arm,arm-v8";
118 enable-method = "psci";
119 reg = <10>;
120 };
121 cpu@11 {
122 device_type = "cpu";
123 compatible = "arm,arm-v8";
124 enable-method = "psci";
125 reg = <11>;
126 };
127 cpu@12 {
128 device_type = "cpu";
129 compatible = "arm,arm-v8";
130 enable-method = "psci";
131 reg = <12>;
132 };
133 cpu@13 {
134 device_type = "cpu";
135 compatible = "arm,arm-v8";
136 enable-method = "psci";
137 reg = <13>;
138 };
139 cpu@14 {
140 device_type = "cpu";
141 compatible = "arm,arm-v8";
142 enable-method = "psci";
143 reg = <14>;
144 };
145 cpu@15 {
146 device_type = "cpu";
147 compatible = "arm,arm-v8";
148 enable-method = "psci";
149 reg = <15>;
150 };
151 };
152
153 intc: intc {
154 compatible = "arm,gic-v3";
155 #address-cells = <2>;
156 #size-cells = <2>;
157 #interrupt-cells = <3>;
158 interrupt-controller;
159 reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>;
160 };
161
162 timer {
163 compatible = "arm,armv8-timer";
164 always-on;
165 /* The IRQ type needs to be OR-ed with the CPU mask */
166 interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW
167 GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW
168 GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW
169 GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
170 };
171
172 uart@2e8 {
173 compatible = "ns16550a";
174 reg = <0x00 0x2e8 0x00 0x8>;
175 clock-frequency = <0x1c2000>;
176 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
177 };
178
179 uart@2f8 {
180 compatible = "ns16550a";
181 reg = <0x00 0x2f8 0x00 0x8>;
182 clock-frequency = <0x1c2000>;
183 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
184 };
185
186 uart@3e8 {
187 compatible = "ns16550a";
188 reg = <0x00 0x3e8 0x00 0x8>;
189 clock-frequency = <0x1c2000>;
190 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
191 };
192
193 uart@3f8 {
194 compatible = "ns16550a";
195 reg = <0x00 0x3f8 0x00 0x8>;
196 clock-frequency = <0x1c2000>;
197 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
198 };
199
200 psci {
201 compatible = "arm,psci-1.0";
202 method = "hvc";
203 };
204
205 pci {
206 compatible = "pci-host-cam-generic";
207 device_type = "pci";
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 dma-coherent;
212 memory-region = <&swiotlb>;
213 ranges = <
214 0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000
215 0x3000000 PLACEHOLDER2 PLACEHOLDER2 PLACEHOLDER2
216 >;
217 bus-range = <0x00 0x00>;
218 reg = <0x00 0x10000 0x00 0x1000000>;
219 interrupt-map = <
Jiyong Parka503f422023-03-21 19:27:04 +0900220 0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH
221 0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH
222 0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH
223 0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH
224 0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH
225 0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH
226 0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH
227 0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH
Nikita Ioffe85d80262023-07-12 17:34:07 +0100228 0x4800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 8) IRQ_TYPE_LEVEL_HIGH
229 0x5000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 9) IRQ_TYPE_LEVEL_HIGH
Jiyong Park196115b2023-02-25 02:01:15 +0900230 >;
231 interrupt-map-mask = <0xf800 0x0 0x0 0x7
232 0xf800 0x0 0x0 0x7
233 0xf800 0x0 0x0 0x7
234 0xf800 0x0 0x0 0x7
235 0xf800 0x0 0x0 0x7
236 0xf800 0x0 0x0 0x7
Jiyong Parka503f422023-03-21 19:27:04 +0900237 0xf800 0x0 0x0 0x7
Nikita Ioffe85d80262023-07-12 17:34:07 +0100238 0xf800 0x0 0x0 0x7
239 0xf800 0x0 0x0 0x7
Jiyong Park196115b2023-02-25 02:01:15 +0900240 0xf800 0x0 0x0 0x7>;
241 };
242
243 clk: pclk@3M {
244 compatible = "fixed-clock";
245 clock-frequency = <0x2fefd8>;
246 #clock-cells = <0>;
247 };
248
249 rtc@2000 {
250 compatible = "arm,primecell";
251 arm,primecell-periphid = <0x41030>;
252 reg = <0x00 0x2000 0x00 0x1000>;
253 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
254 clock-names = "apb_pclk";
255 clocks = <&clk>;
256 };
Sebastian Ene21d12bf2023-03-14 11:04:58 +0000257
258 vmwdt@3000 {
259 compatible = "qemu,vcpu-stall-detector";
260 reg = <0x00 0x3000 0x00 0x1000>;
261 clock-frequency = <10>;
262 timeout-sec = <8>;
263 };
Jaewan Kim96411e92023-11-13 15:54:02 +0900264
265 pviommu_0: pviommu0 {
266 compatible = "pkvm,pviommu";
267 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900268 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900269 };
270
271 pviommu_1: pviommu1 {
272 compatible = "pkvm,pviommu";
273 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900274 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900275 };
276
277 pviommu_2: pviommu2 {
278 compatible = "pkvm,pviommu";
279 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900280 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900281 };
282
283 pviommu_3: pviommu3 {
284 compatible = "pkvm,pviommu";
285 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900286 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900287 };
288
289 pviommu_4: pviommu4 {
290 compatible = "pkvm,pviommu";
291 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900292 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900293 };
294
295 pviommu_5: pviommu5 {
296 compatible = "pkvm,pviommu";
297 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900298 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900299 };
300
301 pviommu_6: pviommu6 {
302 compatible = "pkvm,pviommu";
303 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900304 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900305 };
306
307 pviommu_7: pviommu7 {
308 compatible = "pkvm,pviommu";
309 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900310 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900311 };
312
313 pviommu_8: pviommu8 {
314 compatible = "pkvm,pviommu";
315 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900316 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900317 };
318
319 pviommu_9: pviommu9 {
320 compatible = "pkvm,pviommu";
321 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900322 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900323 };
Jiyong Park196115b2023-02-25 02:01:15 +0900324};