blob: cbda4480b6d32f1dcc5f57cbe8b026bbadb4e042 [file] [log] [blame]
Andrew Walbran5db32352022-05-06 13:58:11 +00001/*
2 * Copyright 2022 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * https://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17.macro mov_i, reg:req, imm:req
18 movz \reg, :abs_g3:\imm
19 movk \reg, :abs_g2_nc:\imm
20 movk \reg, :abs_g1_nc:\imm
21 movk \reg, :abs_g0_nc:\imm
22.endm
23
24/* Stage 1 instruction access cacheability is unaffected. */
25.set .L_SCTLR_ELx_I, 0x1 << 12
26/* SETEND instruction disabled at EL0 in aarch32 mode. */
27.set .L_SCTLR_EL1_SED, 0x1 << 8
28/* Various IT instructions are disabled at EL0 in aarch32 mode. */
29.set .L_SCTLR_EL1_ITD, 0x1 << 7
30.set .L_SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29)
31.set .Lsctlrval, .L_SCTLR_ELx_I | .L_SCTLR_EL1_SED | .L_SCTLR_EL1_ITD | .L_SCTLR_EL1_RES1
32
33/**
34 * Disable the exception vector, caches and page talbe and then jump to the payload at the given
35 * address, passing it the given FDT pointer.
36 *
37 * x0: FDT address to pass to payload
38 * x1: Payload address
39 */
40.global start_payload
41start_payload:
42 /* Move payload address to a higher register and zero out parameters other than x0. */
43 mov x30, x1
44 mov x1, #0
45 mov x2, #0
46 mov x3, #0
47
48 /* Zero out remaining registers to avoid leaking data. */
49 mov x4, #0
50 mov x5, #0
51 mov x6, #0
52 mov x7, #0
53 mov x8, #0
54 mov x9, #0
55 mov x10, #0
56 mov x11, #0
57 mov x12, #0
58 mov x13, #0
59 mov x14, #0
60 mov x15, #0
61 mov x16, #0
62 mov x17, #0
63 mov x18, #0
64 mov x19, #0
65 mov x20, #0
66 mov x21, #0
67 mov x22, #0
68 mov x23, #0
69 mov x24, #0
70 mov x25, #0
71 mov x26, #0
72 mov x27, #0
73 mov x28, #0
74
75 /* Disable the MMU and cache, and set other settings to valid warm reset values. */
76 mov_i x29, .Lsctlrval
77 msr sctlr_el1, x29
78 isb
79 msr ttbr0_el1, xzr
80
81 isb
82 dsb nsh
83
84 /* Jump into the payload. */
85 br x30