Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #define LOG_TAG "hwcomposer-drm" |
| 18 | |
| 19 | #include <fcntl.h> |
| 20 | #include <errno.h> |
| 21 | #include <sys/param.h> |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 22 | #include <sys/resource.h> |
| 23 | #include <pthread.h> |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 24 | #include <queue> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 25 | |
| 26 | #include <cutils/log.h> |
| 27 | |
| 28 | #include <xf86drm.h> |
| 29 | #include <xf86drmMode.h> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 30 | |
| 31 | #include <hardware/hardware.h> |
| 32 | #include <hardware/hwcomposer.h> |
| 33 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 34 | #include <sync/sync.h> |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 35 | #include <sw_sync.h> |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 36 | |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 37 | #include "drm_hwcomposer.h" |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 38 | |
| 39 | #define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0])) |
| 40 | |
| 41 | #define HWCOMPOSER_DRM_DEVICE "/dev/dri/card0" |
| 42 | #define MAX_NUM_DISPLAYS 3 |
| 43 | #define UM_PER_INCH 25400 |
| 44 | |
| 45 | static const uint32_t panel_types[] = { |
| 46 | DRM_MODE_CONNECTOR_LVDS, |
| 47 | DRM_MODE_CONNECTOR_eDP, |
| 48 | DRM_MODE_CONNECTOR_DSI, |
| 49 | }; |
| 50 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 51 | struct hwc_worker { |
| 52 | pthread_t thread; |
| 53 | pthread_mutex_t lock; |
| 54 | pthread_cond_t cond; |
| 55 | bool exit; |
| 56 | }; |
| 57 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 58 | struct hwc_drm_display { |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 59 | struct hwc_context_t *ctx; |
| 60 | int display; |
| 61 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 62 | uint32_t connector_id; |
| 63 | |
| 64 | drmModeModeInfoPtr configs; |
| 65 | uint32_t num_configs; |
| 66 | |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 67 | drmModeModeInfo active_mode; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 68 | uint32_t active_crtc; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 69 | int active_pipe; |
Sean Paul | efb20cb | 2015-02-04 09:29:15 -0800 | [diff] [blame] | 70 | bool initial_modeset_required; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 71 | |
| 72 | struct hwc_worker set_worker; |
| 73 | |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 74 | std::queue<struct hwc_drm_bo> buf_queue; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 75 | struct hwc_drm_bo front; |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 76 | |
| 77 | int timeline_fd; |
| 78 | unsigned timeline_next; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 79 | |
| 80 | struct hwc_worker vsync_worker; |
| 81 | bool enable_vsync_events; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | struct hwc_context_t { |
| 85 | hwc_composer_device_1_t device; |
| 86 | |
| 87 | int fd; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 88 | |
| 89 | hwc_procs_t const *procs; |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 90 | struct hwc_import_context *import_ctx; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 91 | |
| 92 | struct hwc_drm_display displays[MAX_NUM_DISPLAYS]; |
| 93 | int num_displays; |
| 94 | }; |
| 95 | |
| 96 | static int hwc_get_drm_display(struct hwc_context_t *ctx, int display, |
| 97 | struct hwc_drm_display **hd) |
| 98 | { |
| 99 | if (display >= MAX_NUM_DISPLAYS) { |
| 100 | ALOGE("Requested display is out-of-bounds %d %d", display, |
| 101 | MAX_NUM_DISPLAYS); |
| 102 | return -EINVAL; |
| 103 | } |
| 104 | *hd = &ctx->displays[display]; |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static int hwc_prepare_layer(hwc_layer_1_t *layer) |
| 109 | { |
| 110 | /* TODO: We can't handle background right now, defer to sufaceFlinger */ |
| 111 | if (layer->compositionType == HWC_BACKGROUND) { |
| 112 | layer->compositionType = HWC_FRAMEBUFFER; |
| 113 | ALOGV("Can't handle background layers yet"); |
| 114 | |
| 115 | /* TODO: Support sideband compositions */ |
| 116 | } else if (layer->compositionType == HWC_SIDEBAND) { |
| 117 | layer->compositionType = HWC_FRAMEBUFFER; |
| 118 | ALOGV("Can't handle sideband content yet"); |
| 119 | } |
| 120 | |
| 121 | layer->hints = 0; |
| 122 | |
| 123 | /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */ |
| 124 | if (layer->flags & HWC_IS_CURSOR_LAYER) { |
| 125 | ALOGV("Can't handle async cursors yet"); |
| 126 | } |
| 127 | |
| 128 | /* TODO: Handle transformations */ |
| 129 | if (layer->transform) { |
| 130 | ALOGV("Can't handle transformations yet"); |
| 131 | } |
| 132 | |
| 133 | /* TODO: Handle blending & plane alpha*/ |
| 134 | if (layer->blending == HWC_BLENDING_PREMULT || |
| 135 | layer->blending == HWC_BLENDING_COVERAGE) { |
| 136 | ALOGV("Can't handle blending yet"); |
| 137 | } |
| 138 | |
| 139 | /* TODO: Handle cropping & scaling */ |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | static int hwc_prepare(hwc_composer_device_1_t */* dev */, size_t num_displays, |
| 145 | hwc_display_contents_1_t** display_contents) |
| 146 | { |
| 147 | int ret = 0, i, j; |
| 148 | |
| 149 | /* TODO: Check flags for HWC_GEOMETRY_CHANGED */ |
| 150 | |
| 151 | for (i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; i++) { |
| 152 | for (j = 0; j < (int)display_contents[i]->numHwLayers; j++) { |
| 153 | ret = hwc_prepare_layer( |
| 154 | &display_contents[i]->hwLayers[j]); |
| 155 | if (ret) { |
| 156 | ALOGE("Failed to prepare layer %d:%d", j, i); |
| 157 | return ret; |
| 158 | } |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | return ret; |
| 163 | } |
| 164 | |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 165 | /* |
| 166 | * TODO: This hack allows us to use the importer's fd to drm to add and remove |
| 167 | * framebuffers. The reason it exists is because gralloc doesn't export its |
| 168 | * bo's, so we have to use its file descriptor to drm for some operations. Once |
| 169 | * gralloc behaves, we can remove this. |
| 170 | */ |
| 171 | static int hwc_get_fd_for_bo(struct hwc_context_t *ctx, struct hwc_drm_bo *bo) |
| 172 | { |
| 173 | if (bo->importer_fd >= 0) |
| 174 | return bo->importer_fd; |
| 175 | |
| 176 | return ctx->fd; |
| 177 | } |
| 178 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 179 | static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) |
| 180 | { |
| 181 | return a->clock == b->clock && |
| 182 | a->hdisplay == b->hdisplay && |
| 183 | a->hsync_start == b->hsync_start && |
| 184 | a->hsync_end == b->hsync_end && |
| 185 | a->htotal == b->htotal && |
| 186 | a->hskew == b->hskew && |
| 187 | a->vdisplay == b->vdisplay && |
| 188 | a->vsync_start == b->vsync_start && |
| 189 | a->vsync_end == b->vsync_end && |
| 190 | a->vtotal == b->vtotal && |
| 191 | a->vscan == b->vscan && |
| 192 | a->vrefresh == b->vrefresh && |
| 193 | a->flags == b->flags && |
| 194 | a->type == b->type && |
| 195 | !strcmp(a->name, b->name); |
| 196 | } |
| 197 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 198 | static int hwc_modeset_required(struct hwc_drm_display *hd, |
| 199 | bool *modeset_required) |
| 200 | { |
| 201 | drmModeCrtcPtr crtc; |
| 202 | drmModeModeInfoPtr m; |
| 203 | |
Sean Paul | efb20cb | 2015-02-04 09:29:15 -0800 | [diff] [blame] | 204 | if (hd->initial_modeset_required) { |
| 205 | *modeset_required = true; |
| 206 | hd->initial_modeset_required = false; |
| 207 | return 0; |
| 208 | } |
| 209 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 210 | crtc = drmModeGetCrtc(hd->ctx->fd, hd->active_crtc); |
| 211 | if (!crtc) { |
| 212 | ALOGE("Failed to get crtc for display %d", hd->display); |
| 213 | return -ENODEV; |
| 214 | } |
| 215 | |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 216 | m = &hd->active_mode; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 217 | |
| 218 | /* Do a modeset if we haven't done one, or the mode has changed */ |
| 219 | if (!crtc->mode_valid || !hwc_mode_is_equal(m, &crtc->mode)) |
| 220 | *modeset_required = true; |
| 221 | else |
| 222 | *modeset_required = false; |
| 223 | |
| 224 | drmModeFreeCrtc(crtc); |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | static void hwc_flip_handler(int /* fd */, unsigned int /* sequence */, |
| 230 | unsigned int /* tv_sec */, unsigned int /* tv_usec */, |
| 231 | void */* user_data */) |
| 232 | { |
| 233 | } |
| 234 | |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 235 | static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 236 | { |
| 237 | fd_set fds; |
| 238 | drmEventContext event_context; |
| 239 | int ret; |
| 240 | bool modeset_required; |
| 241 | |
| 242 | ret = hwc_modeset_required(hd, &modeset_required); |
| 243 | if (ret) { |
| 244 | ALOGE("Failed to determine if modeset is required %d", ret); |
| 245 | return ret; |
| 246 | } |
| 247 | if (modeset_required) { |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 248 | ret = drmModeSetCrtc(hd->ctx->fd, hd->active_crtc, buf->fb_id, |
| 249 | 0, 0, &hd->connector_id, 1, |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 250 | &hd->active_mode); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 251 | if (ret) { |
| 252 | ALOGE("Modeset failed for crtc %d", |
| 253 | hd->active_crtc); |
| 254 | return ret; |
| 255 | } |
| 256 | return 0; |
| 257 | } |
| 258 | |
| 259 | FD_ZERO(&fds); |
| 260 | FD_SET(hd->ctx->fd, &fds); |
| 261 | |
| 262 | event_context.version = DRM_EVENT_CONTEXT_VERSION; |
| 263 | event_context.page_flip_handler = hwc_flip_handler; |
| 264 | |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 265 | ret = drmModePageFlip(hd->ctx->fd, hd->active_crtc, buf->fb_id, |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 266 | DRM_MODE_PAGE_FLIP_EVENT, hd); |
| 267 | if (ret) { |
| 268 | ALOGE("Failed to flip buffer for crtc %d", |
| 269 | hd->active_crtc); |
| 270 | return ret; |
| 271 | } |
| 272 | |
| 273 | do { |
| 274 | ret = select(hd->ctx->fd + 1, &fds, NULL, NULL, NULL); |
| 275 | } while (ret == -1 && errno == EINTR); |
| 276 | |
| 277 | if (ret != 1) { |
| 278 | ALOGE("Failed waiting for flip to complete\n"); |
| 279 | return -EINVAL; |
| 280 | } |
| 281 | drmHandleEvent(hd->ctx->fd, &event_context); |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 286 | static int hwc_wait_and_set(struct hwc_drm_display *hd, |
| 287 | struct hwc_drm_bo *buf) |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 288 | { |
| 289 | int ret; |
| 290 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 291 | ret = drmModeAddFB2(hwc_get_fd_for_bo(hd->ctx, buf), buf->width, |
| 292 | buf->height, buf->format, buf->gem_handles, buf->pitches, |
| 293 | buf->offsets, &buf->fb_id, 0); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 294 | if (ret) { |
| 295 | ALOGE("could not create drm fb %d", ret); |
| 296 | return ret; |
| 297 | } |
| 298 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 299 | if (buf->acquire_fence_fd >= 0) { |
| 300 | ret = sync_wait(buf->acquire_fence_fd, -1); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 301 | if (ret) { |
| 302 | ALOGE("Failed to wait for acquire %d", ret); |
| 303 | return ret; |
| 304 | } |
| 305 | } |
| 306 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 307 | ret = hwc_flip(hd, buf); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 308 | if (ret) { |
| 309 | ALOGE("Failed to perform flip\n"); |
| 310 | return ret; |
| 311 | } |
| 312 | |
| 313 | if (hd->front.fb_id) { |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 314 | ret = drmModeRmFB(hwc_get_fd_for_bo(hd->ctx, &hd->front), |
| 315 | hd->front.fb_id); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 316 | if (ret) { |
| 317 | ALOGE("Failed to rm fb from front %d", ret); |
| 318 | return ret; |
| 319 | } |
| 320 | } |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 321 | hd->front = *buf; |
| 322 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 323 | return ret; |
| 324 | } |
| 325 | |
| 326 | static void *hwc_set_worker(void *arg) |
| 327 | { |
| 328 | struct hwc_drm_display *hd = (struct hwc_drm_display *)arg; |
| 329 | int ret; |
| 330 | |
| 331 | setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); |
| 332 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 333 | do { |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 334 | struct hwc_drm_bo buf; |
| 335 | |
| 336 | ret = pthread_mutex_lock(&hd->set_worker.lock); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 337 | if (ret) { |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 338 | ALOGE("Failed to lock set lock %d", ret); |
| 339 | return NULL; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 340 | } |
| 341 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 342 | if (hd->set_worker.exit) |
| 343 | goto out; |
| 344 | |
| 345 | if (hd->buf_queue.empty()) { |
| 346 | ret = pthread_cond_wait(&hd->set_worker.cond, |
| 347 | &hd->set_worker.lock); |
| 348 | if (ret) { |
| 349 | ALOGE("Failed to wait on condition %d", ret); |
| 350 | goto out; |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | buf = hd->buf_queue.front(); |
| 355 | hd->buf_queue.pop(); |
| 356 | |
| 357 | ret = pthread_mutex_unlock(&hd->set_worker.lock); |
| 358 | if (ret) { |
| 359 | ALOGE("Failed to unlock set lock %d", ret); |
| 360 | return NULL; |
| 361 | } |
| 362 | |
| 363 | ret = hwc_wait_and_set(hd, &buf); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 364 | if (ret) |
| 365 | ALOGE("Failed to wait and set %d", ret); |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 366 | |
| 367 | ret = sw_sync_timeline_inc(hd->timeline_fd, 1); |
| 368 | if (ret) |
| 369 | ALOGE("Failed to increment sync timeline %d", ret); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 370 | } while (true); |
| 371 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 372 | out: |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 373 | ret = pthread_mutex_unlock(&hd->set_worker.lock); |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 374 | if (ret) |
| 375 | ALOGE("Failed to unlock set lock while exiting %d", ret); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 376 | |
| 377 | return NULL; |
| 378 | } |
| 379 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 380 | static int hwc_set_display(hwc_context_t *ctx, int display, |
| 381 | hwc_display_contents_1_t* display_contents) |
| 382 | { |
| 383 | struct hwc_drm_display *hd = NULL; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 384 | hwc_layer_1_t *layer = NULL; |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 385 | struct hwc_drm_bo buf; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 386 | int ret, i; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 387 | uint32_t fb_id; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 388 | |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 389 | memset(&buf, 0, sizeof(buf)); |
| 390 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 391 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 392 | if (ret) |
| 393 | return ret; |
| 394 | |
| 395 | if (!hd->active_crtc) { |
| 396 | ALOGE("There is no active crtc for display %d", display); |
| 397 | return -ENOENT; |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * TODO: We can only support one hw layer atm, so choose either the |
| 402 | * first one or the framebuffer target. |
| 403 | */ |
| 404 | if (!display_contents->numHwLayers) { |
| 405 | return 0; |
| 406 | } else if (display_contents->numHwLayers == 1) { |
| 407 | layer = &display_contents->hwLayers[0]; |
| 408 | } else { |
| 409 | for (i = 0; i < (int)display_contents->numHwLayers; i++) { |
| 410 | layer = &display_contents->hwLayers[i]; |
| 411 | if (layer->compositionType == HWC_FRAMEBUFFER_TARGET) |
| 412 | break; |
| 413 | } |
| 414 | if (i == (int)display_contents->numHwLayers) { |
| 415 | ALOGE("Could not find a suitable layer for display %d", |
| 416 | display); |
| 417 | } |
| 418 | } |
| 419 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 420 | ret = hwc_create_bo_from_import(ctx->fd, ctx->import_ctx, layer->handle, |
| 421 | &buf); |
| 422 | if (ret) { |
| 423 | ALOGE("Failed to import handle to drm bo %d", ret); |
| 424 | return ret; |
| 425 | } |
| 426 | buf.acquire_fence_fd = layer->acquireFenceFd; |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 427 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 428 | ret = pthread_mutex_lock(&hd->set_worker.lock); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 429 | if (ret) { |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 430 | ALOGE("Failed to lock set lock in set() %d", ret); |
| 431 | return ret; |
| 432 | } |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 433 | |
| 434 | /* |
| 435 | * TODO: Retire and release can use the same sync point here b/c hwc is |
| 436 | * restricted to one layer. Once that is no longer true, this will need |
| 437 | * to change |
| 438 | */ |
| 439 | hd->timeline_next++; |
| 440 | display_contents->retireFenceFd = sw_sync_fence_create(hd->timeline_fd, |
| 441 | "drm_hwc_retire", hd->timeline_next); |
| 442 | layer->releaseFenceFd = sw_sync_fence_create(hd->timeline_fd, |
| 443 | "drm_hwc_release", hd->timeline_next); |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 444 | hd->buf_queue.push(buf); |
| 445 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 446 | ret = pthread_cond_signal(&hd->set_worker.cond); |
| 447 | if (ret) { |
| 448 | ALOGE("Failed to signal set worker %d", ret); |
| 449 | goto out; |
| 450 | } |
| 451 | |
| 452 | ret = pthread_mutex_unlock(&hd->set_worker.lock); |
| 453 | if (ret) { |
| 454 | ALOGE("Failed to unlock set lock in set() %d", ret); |
| 455 | return ret; |
| 456 | } |
| 457 | |
| 458 | return ret; |
| 459 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 460 | out: |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 461 | if (pthread_mutex_unlock(&hd->set_worker.lock)) |
| 462 | ALOGE("Failed to unlock set lock in set error handler"); |
| 463 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 464 | return ret; |
| 465 | } |
| 466 | |
| 467 | static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays, |
| 468 | hwc_display_contents_1_t** display_contents) |
| 469 | { |
| 470 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 471 | int ret = 0, i; |
| 472 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 473 | for (i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; i++) { |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 474 | ret = hwc_set_display(ctx, i, display_contents[i]); |
| 475 | } |
| 476 | |
| 477 | return ret; |
| 478 | } |
| 479 | |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 480 | static int hwc_wait_for_vsync(struct hwc_drm_display *hd) |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 481 | { |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 482 | drmVBlank vblank; |
| 483 | int ret; |
| 484 | uint32_t high_crtc; |
| 485 | int64_t timestamp; |
| 486 | |
| 487 | if (hd->active_pipe == -1) |
| 488 | return -EINVAL; |
| 489 | |
| 490 | memset(&vblank, 0, sizeof(vblank)); |
| 491 | |
| 492 | high_crtc = (hd->active_pipe << DRM_VBLANK_HIGH_CRTC_SHIFT); |
| 493 | vblank.request.type = (drmVBlankSeqType)(DRM_VBLANK_RELATIVE | |
| 494 | (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK)); |
| 495 | vblank.request.sequence = 1; |
| 496 | |
| 497 | ret = drmWaitVBlank(hd->ctx->fd, &vblank); |
| 498 | if (ret) { |
| 499 | ALOGE("Failed to wait for vblank %d", ret); |
| 500 | return ret; |
| 501 | } |
| 502 | |
| 503 | if (hd->ctx->procs->vsync) { |
| 504 | timestamp = vblank.reply.tval_sec * 1000 * 1000 * 1000 + |
| 505 | vblank.reply.tval_usec * 1000; |
| 506 | hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp); |
| 507 | } |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | static void *hwc_vsync_worker(void *arg) |
| 513 | { |
| 514 | struct hwc_drm_display *hd = (struct hwc_drm_display *)arg; |
| 515 | struct hwc_worker *w = &hd->vsync_worker; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 516 | int ret; |
| 517 | |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 518 | setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); |
| 519 | |
| 520 | do { |
| 521 | ret = pthread_mutex_lock(&w->lock); |
| 522 | if (ret) { |
| 523 | ALOGE("Failed to lock vsync lock %d", ret); |
| 524 | return NULL; |
| 525 | } |
| 526 | |
| 527 | if (hd->active_pipe == -1) { |
| 528 | ALOGE("Pipe is no longer active, disable events"); |
| 529 | hd->enable_vsync_events = false; |
| 530 | } |
| 531 | |
| 532 | if (!hd->enable_vsync_events) { |
| 533 | ret = pthread_cond_wait(&w->cond, &w->lock); |
| 534 | if (ret) { |
| 535 | ALOGE("Failed to wait on vsync cond %d", ret); |
| 536 | break; |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | if (w->exit) |
| 541 | break; |
| 542 | |
| 543 | ret = pthread_mutex_unlock(&w->lock); |
| 544 | if (ret) { |
| 545 | ALOGE("Failed to unlock vsync lock %d", ret); |
| 546 | return NULL; |
| 547 | } |
| 548 | |
| 549 | if (!hd->enable_vsync_events) |
| 550 | continue; |
| 551 | |
| 552 | ret = hwc_wait_for_vsync(hd); |
| 553 | if (ret) |
| 554 | ALOGE("Failed to wait for vsync %d", ret); |
| 555 | |
| 556 | } while (true); |
| 557 | |
| 558 | out: |
| 559 | ret = pthread_mutex_unlock(&hd->set_worker.lock); |
| 560 | if (ret) |
| 561 | ALOGE("Failed to unlock set lock while exiting %d", ret); |
| 562 | |
| 563 | return NULL; |
| 564 | } |
| 565 | |
| 566 | static int hwc_event_control(struct hwc_composer_device_1* dev, int display, |
| 567 | int event, int enabled) |
| 568 | { |
| 569 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 570 | struct hwc_drm_display *hd = NULL; |
| 571 | int ret; |
| 572 | |
| 573 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 574 | if (ret) |
| 575 | return ret; |
| 576 | |
| 577 | if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1)) |
| 578 | return -EINVAL; |
| 579 | |
| 580 | if (hd->active_pipe == -1) { |
| 581 | ALOGD("Can't service events for display %d, no pipe", display); |
| 582 | return -EINVAL; |
| 583 | } |
| 584 | |
| 585 | ret = pthread_mutex_lock(&hd->vsync_worker.lock); |
| 586 | if (ret) { |
| 587 | ALOGE("Failed to lock vsync lock %d", ret); |
| 588 | return ret; |
| 589 | } |
| 590 | |
| 591 | hd->enable_vsync_events = !!enabled; |
| 592 | |
| 593 | ret = pthread_cond_signal(&hd->vsync_worker.cond); |
| 594 | if (ret) { |
| 595 | ALOGE("Failed to signal vsync thread %d", ret); |
| 596 | goto out; |
| 597 | } |
| 598 | |
| 599 | ret = pthread_mutex_unlock(&hd->vsync_worker.lock); |
| 600 | if (ret) { |
| 601 | ALOGE("Failed to unlock vsync lock %d", ret); |
| 602 | return ret; |
| 603 | } |
| 604 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 605 | return 0; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 606 | |
| 607 | out: |
| 608 | if (pthread_mutex_unlock(&hd->vsync_worker.lock)) |
| 609 | ALOGE("Failed to unlock vsync worker in error path"); |
| 610 | |
| 611 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | static int hwc_set_power_mode(struct hwc_composer_device_1* dev, int display, |
| 615 | int mode) |
| 616 | { |
| 617 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 618 | struct hwc_drm_display *hd = NULL; |
| 619 | drmModeConnectorPtr c; |
| 620 | int ret, i; |
| 621 | uint32_t dpms_prop = 0; |
| 622 | uint64_t dpms_value = 0; |
| 623 | |
| 624 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 625 | if (ret) |
| 626 | return ret; |
| 627 | |
| 628 | c = drmModeGetConnector(ctx->fd, hd->connector_id); |
| 629 | if (!c) { |
| 630 | ALOGE("Failed to get connector %d", display); |
| 631 | return -ENODEV; |
| 632 | } |
| 633 | |
| 634 | for (i = 0; !dpms_prop && i < c->count_props; i++) { |
| 635 | drmModePropertyPtr p; |
| 636 | |
| 637 | p = drmModeGetProperty(ctx->fd, c->props[i]); |
| 638 | if (!p) |
| 639 | continue; |
| 640 | |
| 641 | if (!strcmp(p->name, "DPMS")) |
| 642 | dpms_prop = c->props[i]; |
| 643 | |
| 644 | drmModeFreeProperty(p); |
| 645 | } |
| 646 | if (!dpms_prop) { |
| 647 | ALOGE("Failed to get DPMS property from display %d", display); |
| 648 | ret = -ENOENT; |
| 649 | goto out; |
| 650 | } |
| 651 | |
| 652 | switch(mode) { |
| 653 | case HWC_POWER_MODE_OFF: |
| 654 | dpms_value = DRM_MODE_DPMS_OFF; |
| 655 | break; |
| 656 | |
| 657 | /* We can't support dozing right now, so go full on */ |
| 658 | case HWC_POWER_MODE_DOZE: |
| 659 | case HWC_POWER_MODE_DOZE_SUSPEND: |
| 660 | case HWC_POWER_MODE_NORMAL: |
| 661 | dpms_value = DRM_MODE_DPMS_ON; |
| 662 | break; |
| 663 | }; |
| 664 | |
| 665 | ret = drmModeConnectorSetProperty(ctx->fd, c->connector_id, |
| 666 | dpms_prop, dpms_value); |
| 667 | if (ret) { |
| 668 | ALOGE("Failed to set DPMS property for display %d", display); |
| 669 | goto out; |
| 670 | } |
| 671 | |
| 672 | out: |
| 673 | drmModeFreeConnector(c); |
| 674 | return ret; |
| 675 | } |
| 676 | |
| 677 | static int hwc_query(struct hwc_composer_device_1 */* dev */, int what, |
| 678 | int *value) |
| 679 | { |
| 680 | switch(what) { |
| 681 | case HWC_BACKGROUND_LAYER_SUPPORTED: |
| 682 | *value = 0; /* TODO: We should do this */ |
| 683 | break; |
| 684 | case HWC_VSYNC_PERIOD: |
| 685 | ALOGW("Query for deprecated vsync value, returning 60Hz"); |
| 686 | *value = 1000 * 1000 * 1000 / 60; |
| 687 | break; |
| 688 | case HWC_DISPLAY_TYPES_SUPPORTED: |
| 689 | *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL; |
| 690 | break; |
| 691 | } |
| 692 | return 0; |
| 693 | } |
| 694 | |
| 695 | static void hwc_register_procs(struct hwc_composer_device_1* dev, |
| 696 | hwc_procs_t const* procs) |
| 697 | { |
| 698 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 699 | |
| 700 | ctx->procs = procs; |
| 701 | } |
| 702 | |
| 703 | static int hwc_get_display_configs(struct hwc_composer_device_1* dev, |
| 704 | int display, uint32_t* configs, size_t* numConfigs) |
| 705 | { |
| 706 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 707 | struct hwc_drm_display *hd = NULL; |
| 708 | drmModeConnectorPtr c; |
| 709 | int ret = 0, i; |
| 710 | |
| 711 | if (!*numConfigs) |
| 712 | return 0; |
| 713 | |
| 714 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 715 | if (ret) |
| 716 | return ret; |
| 717 | |
| 718 | c = drmModeGetConnector(ctx->fd, hd->connector_id); |
| 719 | if (!c) { |
| 720 | ALOGE("Failed to get connector %d", display); |
| 721 | return -ENODEV; |
| 722 | } |
| 723 | |
Sean Paul | a4283c5 | 2015-02-04 10:08:00 -0800 | [diff] [blame^] | 724 | if (hd->configs) { |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 725 | free(hd->configs); |
Sean Paul | a4283c5 | 2015-02-04 10:08:00 -0800 | [diff] [blame^] | 726 | hd->configs = NULL; |
| 727 | } |
| 728 | |
| 729 | if (c->connection == DRM_MODE_DISCONNECTED) { |
| 730 | ret = -ENODEV; |
| 731 | goto out; |
| 732 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 733 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 734 | hd->configs = (drmModeModeInfoPtr)calloc(c->count_modes, |
| 735 | sizeof(*hd->configs)); |
| 736 | if (!hd->configs) { |
| 737 | ALOGE("Failed to allocate config list for display %d", display); |
| 738 | ret = -ENOMEM; |
| 739 | hd->num_configs = 0; |
| 740 | goto out; |
| 741 | } |
| 742 | |
| 743 | for (i = 0; i < c->count_modes; i++) { |
| 744 | drmModeModeInfoPtr m = &hd->configs[i]; |
| 745 | |
| 746 | memcpy(m, &c->modes[i], sizeof(*m)); |
| 747 | |
| 748 | if (i < (int)*numConfigs) |
| 749 | configs[i] = i; |
| 750 | } |
| 751 | |
| 752 | hd->num_configs = c->count_modes; |
| 753 | *numConfigs = MIN(c->count_modes, *numConfigs); |
| 754 | |
| 755 | out: |
| 756 | drmModeFreeConnector(c); |
| 757 | return ret; |
| 758 | } |
| 759 | |
| 760 | static int hwc_check_config_valid(struct hwc_context_t *ctx, |
| 761 | drmModeConnectorPtr connector, int display, |
| 762 | int config_idx) |
| 763 | { |
| 764 | struct hwc_drm_display *hd = NULL; |
| 765 | drmModeModeInfoPtr m = NULL; |
| 766 | int ret = 0, i; |
| 767 | |
| 768 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 769 | if (ret) |
| 770 | return ret; |
| 771 | |
| 772 | /* Make sure the requested config is still valid for the display */ |
| 773 | for (i = 0; i < connector->count_modes; i++) { |
| 774 | if (hwc_mode_is_equal(&connector->modes[i], |
| 775 | &hd->configs[config_idx])) { |
| 776 | m = &hd->configs[config_idx]; |
| 777 | break; |
| 778 | } |
| 779 | } |
| 780 | if (!m) |
| 781 | return -ENOENT; |
| 782 | |
| 783 | return 0; |
| 784 | } |
| 785 | |
| 786 | static int hwc_get_display_attributes(struct hwc_composer_device_1* dev, |
| 787 | int display, uint32_t config, const uint32_t* attributes, |
| 788 | int32_t* values) |
| 789 | { |
| 790 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 791 | struct hwc_drm_display *hd = NULL; |
| 792 | drmModeConnectorPtr c; |
| 793 | drmModeModeInfoPtr m; |
| 794 | int ret, i; |
| 795 | |
| 796 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 797 | if (ret) |
| 798 | return ret; |
| 799 | |
| 800 | if (config >= hd->num_configs) { |
| 801 | ALOGE("Requested config is out-of-bounds %d %d", config, |
| 802 | hd->num_configs); |
| 803 | return -EINVAL; |
| 804 | } |
| 805 | |
| 806 | c = drmModeGetConnector(ctx->fd, hd->connector_id); |
| 807 | if (!c) { |
| 808 | ALOGE("Failed to get connector %d", display); |
| 809 | return -ENODEV; |
| 810 | } |
| 811 | |
| 812 | ret = hwc_check_config_valid(ctx, c, display, (int)config); |
| 813 | if (ret) { |
| 814 | ALOGE("Provided config is no longer valid %u", config); |
| 815 | goto out; |
| 816 | } |
| 817 | |
| 818 | m = &hd->configs[config]; |
| 819 | for (i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { |
| 820 | switch(attributes[i]) { |
| 821 | case HWC_DISPLAY_VSYNC_PERIOD: |
| 822 | values[i] = 1000 * 1000 * 1000 / m->vrefresh; |
| 823 | break; |
| 824 | case HWC_DISPLAY_WIDTH: |
| 825 | values[i] = m->hdisplay; |
| 826 | break; |
| 827 | case HWC_DISPLAY_HEIGHT: |
| 828 | values[i] = m->vdisplay; |
| 829 | break; |
| 830 | case HWC_DISPLAY_DPI_X: |
| 831 | /* Dots per 1000 inches */ |
| 832 | values[i] = c->mmWidth ? |
| 833 | (m->hdisplay * UM_PER_INCH) / c->mmWidth : 0; |
| 834 | break; |
| 835 | case HWC_DISPLAY_DPI_Y: |
| 836 | /* Dots per 1000 inches */ |
| 837 | values[i] = c->mmHeight ? |
| 838 | (m->vdisplay * UM_PER_INCH) / c->mmHeight : 0; |
| 839 | break; |
| 840 | } |
| 841 | } |
| 842 | |
| 843 | out: |
| 844 | drmModeFreeConnector(c); |
| 845 | return ret; |
| 846 | } |
| 847 | |
| 848 | static int hwc_get_active_config(struct hwc_composer_device_1* dev, int display) |
| 849 | { |
| 850 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 851 | struct hwc_drm_display *hd = NULL; |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 852 | int ret, i, index = -1; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 853 | |
| 854 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 855 | if (ret) |
| 856 | return ret; |
| 857 | |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 858 | /* Find the current mode in the config list */ |
| 859 | for (i = 0; i < (int)hd->num_configs; i++) { |
| 860 | if (hwc_mode_is_equal(&hd->configs[i], &hd->active_mode)) { |
| 861 | index = i; |
| 862 | break; |
| 863 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 864 | } |
| 865 | |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 866 | return index; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 867 | } |
| 868 | |
| 869 | static bool hwc_crtc_is_bound(struct hwc_context_t *ctx, uint32_t crtc_id) |
| 870 | { |
| 871 | int i; |
| 872 | |
| 873 | for (i = 0; i < MAX_NUM_DISPLAYS; i++) { |
| 874 | if (ctx->displays[i].active_crtc == crtc_id) |
| 875 | return true; |
| 876 | } |
| 877 | return false; |
| 878 | } |
| 879 | |
| 880 | static int hwc_try_encoder(struct hwc_context_t *ctx, drmModeResPtr r, |
| 881 | uint32_t encoder_id, uint32_t *crtc_id) |
| 882 | { |
| 883 | drmModeEncoderPtr e; |
| 884 | int ret, i; |
| 885 | |
| 886 | e = drmModeGetEncoder(ctx->fd, encoder_id); |
| 887 | if (!e) { |
| 888 | ALOGE("Failed to get encoder for connector %d", encoder_id); |
| 889 | return -ENODEV; |
| 890 | } |
| 891 | |
| 892 | /* First try to use the currently-bound crtc */ |
| 893 | if (e->crtc_id) { |
| 894 | if (!hwc_crtc_is_bound(ctx, e->crtc_id)) { |
| 895 | *crtc_id = e->crtc_id; |
| 896 | ret = 0; |
| 897 | goto out; |
| 898 | } |
| 899 | } |
| 900 | |
| 901 | /* Try to find a possible crtc which will work */ |
| 902 | for (i = 0; i < r->count_crtcs; i++) { |
| 903 | if (!(e->possible_crtcs & (1 << i))) |
| 904 | continue; |
| 905 | |
| 906 | /* We've already tried this earlier */ |
| 907 | if (e->crtc_id == r->crtcs[i]) |
| 908 | continue; |
| 909 | |
| 910 | if (!hwc_crtc_is_bound(ctx, r->crtcs[i])) { |
| 911 | *crtc_id = r->crtcs[i]; |
| 912 | ret = 0; |
| 913 | goto out; |
| 914 | } |
| 915 | } |
| 916 | |
| 917 | /* We can't use the encoder, but nothing went wrong, try another one */ |
| 918 | ret = -EAGAIN; |
| 919 | |
| 920 | out: |
| 921 | drmModeFreeEncoder(e); |
| 922 | return ret; |
| 923 | } |
| 924 | |
| 925 | static int hwc_set_active_config(struct hwc_composer_device_1* dev, int display, |
| 926 | int index) |
| 927 | { |
| 928 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 929 | struct hwc_drm_display *hd = NULL; |
| 930 | drmModeResPtr r = NULL; |
| 931 | drmModeConnectorPtr c; |
| 932 | uint32_t crtc_id = 0; |
| 933 | int ret, i; |
| 934 | bool new_crtc, new_encoder; |
| 935 | |
| 936 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 937 | if (ret) |
| 938 | return ret; |
| 939 | |
| 940 | c = drmModeGetConnector(ctx->fd, hd->connector_id); |
| 941 | if (!c) { |
| 942 | ALOGE("Failed to get connector %d", display); |
| 943 | return -ENODEV; |
| 944 | } |
| 945 | |
| 946 | if (c->connection == DRM_MODE_DISCONNECTED) { |
| 947 | ALOGE("Tried to configure a disconnected display %d", display); |
| 948 | ret = -ENODEV; |
| 949 | goto out; |
| 950 | } |
| 951 | |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 952 | if (index >= c->count_modes) { |
| 953 | ALOGE("Index is out-of-bounds %d/%d", index, c->count_modes); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 954 | ret = -ENOENT; |
| 955 | goto out; |
| 956 | } |
| 957 | |
| 958 | r = drmModeGetResources(ctx->fd); |
| 959 | if (!r) { |
| 960 | ALOGE("Failed to get drm resources"); |
| 961 | goto out; |
| 962 | } |
| 963 | |
| 964 | /* We no longer have an active_crtc */ |
| 965 | hd->active_crtc = 0; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 966 | hd->active_pipe = -1; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 967 | |
| 968 | /* First, try to use the currently-connected encoder */ |
| 969 | if (c->encoder_id) { |
| 970 | ret = hwc_try_encoder(ctx, r, c->encoder_id, &crtc_id); |
| 971 | if (ret && ret != -EAGAIN) { |
| 972 | ALOGE("Encoder try failed %d", ret); |
| 973 | goto out; |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | /* We couldn't find a crtc with the attached encoder, try the others */ |
| 978 | if (!crtc_id) { |
| 979 | for (i = 0; i < c->count_encoders; i++) { |
| 980 | ret = hwc_try_encoder(ctx, r, c->encoders[i], &crtc_id); |
| 981 | if (!ret) { |
| 982 | break; |
| 983 | } else if (ret != -EAGAIN) { |
| 984 | ALOGE("Encoder try failed %d", ret); |
| 985 | goto out; |
| 986 | } |
| 987 | } |
| 988 | if (!crtc_id) { |
| 989 | ALOGE("Couldn't find valid crtc to modeset"); |
| 990 | ret = -EINVAL; |
| 991 | goto out; |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | hd->active_crtc = crtc_id; |
Sean Paul | fa406a1 | 2015-02-04 10:05:44 -0800 | [diff] [blame] | 996 | |
| 997 | memcpy(&hd->active_mode, &hd->configs[index], sizeof(hd->active_mode)); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 998 | |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 999 | /* Find the pipe corresponding to the crtc_id */ |
| 1000 | for (i = 0; i < r->count_crtcs; i++) { |
| 1001 | /* We've already tried this earlier */ |
| 1002 | if (r->crtcs[i] == crtc_id) { |
| 1003 | hd->active_pipe = i; |
| 1004 | break; |
| 1005 | } |
| 1006 | } |
| 1007 | /* This should never happen... hehehe */ |
| 1008 | if (hd->active_pipe == -1) { |
| 1009 | ALOGE("Active crtc was not found in resources!!"); |
| 1010 | ret = -ENODEV; |
| 1011 | goto out; |
| 1012 | } |
| 1013 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1014 | /* TODO: Once we have atomic, set the crtc timing info here */ |
| 1015 | |
| 1016 | out: |
| 1017 | if (r) |
| 1018 | drmModeFreeResources(r); |
| 1019 | |
| 1020 | drmModeFreeConnector(c); |
| 1021 | return ret; |
| 1022 | } |
| 1023 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 1024 | static int hwc_destroy_worker(struct hwc_worker *worker) |
| 1025 | { |
| 1026 | int ret; |
| 1027 | |
| 1028 | ret = pthread_mutex_lock(&worker->lock); |
| 1029 | if (ret) { |
| 1030 | ALOGE("Failed to lock in destroy() %d", ret); |
| 1031 | return ret; |
| 1032 | } |
| 1033 | |
| 1034 | worker->exit = true; |
| 1035 | |
| 1036 | ret |= pthread_cond_signal(&worker->cond); |
| 1037 | if (ret) |
| 1038 | ALOGE("Failed to signal cond in destroy() %d", ret); |
| 1039 | |
| 1040 | ret |= pthread_mutex_unlock(&worker->lock); |
| 1041 | if (ret) |
| 1042 | ALOGE("Failed to unlock in destroy() %d", ret); |
| 1043 | |
| 1044 | ret |= pthread_join(worker->thread, NULL); |
| 1045 | if (ret && ret != ESRCH) |
| 1046 | ALOGE("Failed to join thread in destroy() %d", ret); |
| 1047 | |
| 1048 | return ret; |
| 1049 | } |
| 1050 | |
| 1051 | static void hwc_destroy_display(struct hwc_drm_display *hd) |
| 1052 | { |
| 1053 | int ret; |
| 1054 | |
| 1055 | if (hwc_destroy_worker(&hd->set_worker)) |
| 1056 | ALOGE("Destroy set worker failed"); |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 1057 | |
| 1058 | if (hwc_destroy_worker(&hd->vsync_worker)) |
| 1059 | ALOGE("Destroy vsync worker failed"); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 1060 | } |
| 1061 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1062 | static int hwc_device_close(struct hw_device_t *dev) |
| 1063 | { |
| 1064 | struct hwc_context_t *ctx = (struct hwc_context_t *)dev; |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 1065 | int ret, i; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1066 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 1067 | for (i = 0; i < MAX_NUM_DISPLAYS; i++) |
| 1068 | hwc_destroy_display(&ctx->displays[i]); |
| 1069 | |
| 1070 | drmClose(ctx->fd); |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 1071 | |
| 1072 | ret = hwc_import_destroy(ctx->import_ctx); |
| 1073 | if (ret) |
| 1074 | ALOGE("Could not destroy import %d", ret); |
| 1075 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1076 | free(ctx); |
| 1077 | |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 1081 | static int hwc_initialize_worker(struct hwc_drm_display *hd, |
| 1082 | struct hwc_worker *worker, void *(*routine)(void*)) |
| 1083 | { |
| 1084 | int ret; |
| 1085 | |
| 1086 | ret = pthread_cond_init(&worker->cond, NULL); |
| 1087 | if (ret) { |
| 1088 | ALOGE("Failed to create worker condition %d", ret); |
| 1089 | return ret; |
| 1090 | } |
| 1091 | |
| 1092 | ret = pthread_mutex_init(&worker->lock, NULL); |
| 1093 | if (ret) { |
| 1094 | ALOGE("Failed to initialize worker lock %d", ret); |
| 1095 | goto err_cond; |
| 1096 | } |
| 1097 | |
| 1098 | worker->exit = false; |
| 1099 | |
| 1100 | ret = pthread_create(&worker->thread, NULL, routine, hd); |
| 1101 | if (ret) { |
| 1102 | ALOGE("Could not create worker thread %d", ret); |
| 1103 | goto err_lock; |
| 1104 | } |
| 1105 | return 0; |
| 1106 | |
| 1107 | err_lock: |
| 1108 | pthread_mutex_destroy(&worker->lock); |
| 1109 | err_cond: |
| 1110 | pthread_cond_destroy(&worker->cond); |
| 1111 | return ret; |
| 1112 | } |
| 1113 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1114 | static int hwc_initialize_display(struct hwc_context_t *ctx, int display, |
| 1115 | uint32_t connector_id) |
| 1116 | { |
| 1117 | struct hwc_drm_display *hd = NULL; |
| 1118 | int ret; |
| 1119 | |
| 1120 | ret = hwc_get_drm_display(ctx, display, &hd); |
| 1121 | if (ret) |
| 1122 | return ret; |
| 1123 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 1124 | hd->ctx = ctx; |
| 1125 | hd->display = display; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 1126 | hd->active_pipe = -1; |
Sean Paul | efb20cb | 2015-02-04 09:29:15 -0800 | [diff] [blame] | 1127 | hd->initial_modeset_required = true; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1128 | hd->connector_id = connector_id; |
| 1129 | |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 1130 | ret = sw_sync_timeline_create(); |
| 1131 | if (ret < 0) { |
| 1132 | ALOGE("Failed to create sw sync timeline %d", ret); |
| 1133 | return ret; |
| 1134 | } |
| 1135 | hd->timeline_fd = ret; |
| 1136 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 1137 | ret = hwc_initialize_worker(hd, &hd->set_worker, hwc_set_worker); |
| 1138 | if (ret) { |
| 1139 | ALOGE("Failed to create set worker %d\n", ret); |
| 1140 | return ret; |
| 1141 | } |
| 1142 | |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 1143 | ret = hwc_initialize_worker(hd, &hd->vsync_worker, hwc_vsync_worker); |
| 1144 | if (ret) { |
| 1145 | ALOGE("Failed to create vsync worker %d", ret); |
| 1146 | goto err; |
| 1147 | } |
| 1148 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1149 | return 0; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 1150 | |
| 1151 | err: |
| 1152 | if (hwc_destroy_worker(&hd->set_worker)) |
| 1153 | ALOGE("Failed to destroy set worker"); |
| 1154 | |
| 1155 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1156 | } |
| 1157 | |
| 1158 | static int hwc_enumerate_displays(struct hwc_context_t *ctx) |
| 1159 | { |
| 1160 | struct hwc_drm_display *panel_hd; |
| 1161 | drmModeResPtr res; |
| 1162 | drmModeConnectorPtr *conn_list; |
| 1163 | int ret = 0, i, j; |
| 1164 | |
| 1165 | res = drmModeGetResources(ctx->fd); |
| 1166 | if (!res) { |
| 1167 | ALOGE("Failed to get drm resources"); |
| 1168 | return -ENODEV; |
| 1169 | } |
| 1170 | |
| 1171 | conn_list = (drmModeConnector **)calloc(res->count_connectors, |
| 1172 | sizeof(*conn_list)); |
| 1173 | if (!conn_list) { |
| 1174 | ALOGE("Failed to allocate connector list"); |
| 1175 | ret = -ENOMEM; |
| 1176 | goto out; |
| 1177 | } |
| 1178 | |
| 1179 | for (i = 0; i < res->count_connectors; i++) { |
| 1180 | conn_list[i] = drmModeGetConnector(ctx->fd, res->connectors[i]); |
| 1181 | if (!conn_list[i]) { |
| 1182 | ALOGE("Failed to get connector %d", res->connectors[i]); |
| 1183 | ret = -ENODEV; |
| 1184 | goto out; |
| 1185 | } |
| 1186 | } |
| 1187 | |
| 1188 | ctx->num_displays = 0; |
| 1189 | |
| 1190 | /* Find a connected, panel type connector for display 0 */ |
| 1191 | for (i = 0; i < res->count_connectors; i++) { |
| 1192 | drmModeConnectorPtr c = conn_list[i]; |
| 1193 | |
| 1194 | for (j = 0; j < ARRAY_SIZE(panel_types); j++) { |
| 1195 | if (c->connector_type == panel_types[j] && |
| 1196 | c->connection == DRM_MODE_CONNECTED) |
| 1197 | break; |
| 1198 | } |
| 1199 | if (j == ARRAY_SIZE(panel_types)) |
| 1200 | continue; |
| 1201 | |
| 1202 | hwc_initialize_display(ctx, ctx->num_displays, c->connector_id); |
| 1203 | ctx->num_displays++; |
| 1204 | break; |
| 1205 | } |
| 1206 | |
| 1207 | ret = hwc_get_drm_display(ctx, 0, &panel_hd); |
| 1208 | if (ret) |
| 1209 | goto out; |
| 1210 | |
| 1211 | /* Fill in the other displays */ |
| 1212 | for (i = 0; i < res->count_connectors; i++) { |
| 1213 | drmModeConnectorPtr c = conn_list[i]; |
| 1214 | |
| 1215 | if (panel_hd->connector_id == c->connector_id) |
| 1216 | continue; |
| 1217 | |
| 1218 | hwc_initialize_display(ctx, ctx->num_displays, c->connector_id); |
| 1219 | ctx->num_displays++; |
| 1220 | } |
| 1221 | |
| 1222 | out: |
| 1223 | for (i = 0; i < res->count_connectors; i++) { |
| 1224 | if (conn_list[i]) |
| 1225 | drmModeFreeConnector(conn_list[i]); |
| 1226 | } |
| 1227 | free(conn_list); |
| 1228 | |
| 1229 | if (res) |
| 1230 | drmModeFreeResources(res); |
| 1231 | |
| 1232 | return ret; |
| 1233 | } |
| 1234 | |
| 1235 | static int hwc_device_open(const struct hw_module_t* module, const char* name, |
| 1236 | struct hw_device_t** dev) |
| 1237 | { |
| 1238 | int ret = 0; |
| 1239 | struct hwc_context_t *ctx; |
| 1240 | |
| 1241 | if (strcmp(name, HWC_HARDWARE_COMPOSER)) { |
| 1242 | ALOGE("Invalid module name- %s", name); |
| 1243 | return -EINVAL; |
| 1244 | } |
| 1245 | |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 1246 | ctx = new hwc_context_t(); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1247 | if (!ctx) { |
| 1248 | ALOGE("Failed to allocate hwc context"); |
| 1249 | return -ENOMEM; |
| 1250 | } |
| 1251 | |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 1252 | ret = hwc_import_init(&ctx->import_ctx); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1253 | if (ret) { |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 1254 | ALOGE("Failed to initialize import context"); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1255 | goto out; |
| 1256 | } |
| 1257 | |
| 1258 | /* TODO: Use drmOpenControl here instead */ |
| 1259 | ctx->fd = open(HWCOMPOSER_DRM_DEVICE, O_RDWR); |
| 1260 | if (ctx->fd < 0) { |
| 1261 | ALOGE("Failed to open dri- %s", strerror(-errno)); |
| 1262 | goto out; |
| 1263 | } |
| 1264 | |
| 1265 | ret = drmSetMaster(ctx->fd); |
| 1266 | if (ret) { |
| 1267 | ALOGE("Failed to set hwcomposer as drm master %d", ret); |
| 1268 | goto out; |
| 1269 | } |
| 1270 | |
| 1271 | ret = hwc_enumerate_displays(ctx); |
| 1272 | if (ret) { |
| 1273 | ALOGE("Failed to enumerate displays: %s", strerror(ret)); |
| 1274 | goto out; |
| 1275 | } |
| 1276 | |
| 1277 | ctx->device.common.tag = HARDWARE_DEVICE_TAG; |
| 1278 | ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4; |
| 1279 | ctx->device.common.module = const_cast<hw_module_t*>(module); |
| 1280 | ctx->device.common.close = hwc_device_close; |
| 1281 | |
| 1282 | ctx->device.prepare = hwc_prepare; |
| 1283 | ctx->device.set = hwc_set; |
| 1284 | ctx->device.eventControl = hwc_event_control; |
| 1285 | ctx->device.setPowerMode = hwc_set_power_mode; |
| 1286 | ctx->device.query = hwc_query; |
| 1287 | ctx->device.registerProcs = hwc_register_procs; |
| 1288 | ctx->device.getDisplayConfigs = hwc_get_display_configs; |
| 1289 | ctx->device.getDisplayAttributes = hwc_get_display_attributes; |
| 1290 | ctx->device.getActiveConfig = hwc_get_active_config; |
| 1291 | ctx->device.setActiveConfig = hwc_set_active_config; |
| 1292 | ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */ |
| 1293 | |
| 1294 | *dev = &ctx->device.common; |
| 1295 | |
| 1296 | return 0; |
| 1297 | out: |
| 1298 | if (ctx->fd >= 0) |
| 1299 | close(ctx->fd); |
| 1300 | |
| 1301 | free(ctx); |
| 1302 | return ret; |
| 1303 | } |
| 1304 | |
| 1305 | static struct hw_module_methods_t hwc_module_methods = { |
| 1306 | open: hwc_device_open |
| 1307 | }; |
| 1308 | |
| 1309 | hwc_module_t HAL_MODULE_INFO_SYM = { |
| 1310 | common: { |
| 1311 | tag: HARDWARE_MODULE_TAG, |
| 1312 | version_major: 1, |
| 1313 | version_minor: 0, |
| 1314 | id: HWC_HARDWARE_MODULE_ID, |
| 1315 | name: "DRM hwcomposer module", |
| 1316 | author: "The Android Open Source Project", |
| 1317 | methods: &hwc_module_methods, |
| 1318 | dso: NULL, |
| 1319 | reserved: { 0 }, |
| 1320 | } |
| 1321 | }; |