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Christopher Ferris05d08e92016-02-04 13:16:38 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef VIRTIO_GPU_HW_H
20#define VIRTIO_GPU_HW_H
21#include <linux/types.h>
22#define VIRTIO_GPU_F_VIRGL 0
Christopher Ferris05d08e92016-02-04 13:16:38 -080023enum virtio_gpu_ctrl_type {
24 VIRTIO_GPU_UNDEFINED = 0,
25 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
26 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
Christopher Ferris05d08e92016-02-04 13:16:38 -080027 VIRTIO_GPU_CMD_RESOURCE_UNREF,
28 VIRTIO_GPU_CMD_SET_SCANOUT,
29 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
30 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
Christopher Ferris05d08e92016-02-04 13:16:38 -080031 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
32 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
33 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
34 VIRTIO_GPU_CMD_GET_CAPSET,
Christopher Ferris05d08e92016-02-04 13:16:38 -080035 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
36 VIRTIO_GPU_CMD_CTX_DESTROY,
37 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
38 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
Christopher Ferris05d08e92016-02-04 13:16:38 -080039 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
40 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
41 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
42 VIRTIO_GPU_CMD_SUBMIT_3D,
Christopher Ferris05d08e92016-02-04 13:16:38 -080043 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
44 VIRTIO_GPU_CMD_MOVE_CURSOR,
45 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
46 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
Christopher Ferris05d08e92016-02-04 13:16:38 -080047 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
48 VIRTIO_GPU_RESP_OK_CAPSET,
49 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
50 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
Christopher Ferris05d08e92016-02-04 13:16:38 -080051 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
52 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
53 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
54 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
Christopher Ferris05d08e92016-02-04 13:16:38 -080055};
56#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
57struct virtio_gpu_ctrl_hdr {
58 __le32 type;
Christopher Ferris05d08e92016-02-04 13:16:38 -080059 __le32 flags;
60 __le64 fence_id;
61 __le32 ctx_id;
62 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -080063};
64struct virtio_gpu_cursor_pos {
65 __le32 scanout_id;
66 __le32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -080067 __le32 y;
68 __le32 padding;
69};
70struct virtio_gpu_update_cursor {
Christopher Ferris05d08e92016-02-04 13:16:38 -080071 struct virtio_gpu_ctrl_hdr hdr;
72 struct virtio_gpu_cursor_pos pos;
73 __le32 resource_id;
74 __le32 hot_x;
Christopher Ferris05d08e92016-02-04 13:16:38 -080075 __le32 hot_y;
76 __le32 padding;
77};
78struct virtio_gpu_rect {
Christopher Ferris05d08e92016-02-04 13:16:38 -080079 __le32 x;
80 __le32 y;
81 __le32 width;
82 __le32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -080083};
84struct virtio_gpu_resource_unref {
85 struct virtio_gpu_ctrl_hdr hdr;
86 __le32 resource_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -080087 __le32 padding;
88};
89struct virtio_gpu_resource_create_2d {
90 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -080091 __le32 resource_id;
92 __le32 format;
93 __le32 width;
94 __le32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -080095};
96struct virtio_gpu_set_scanout {
97 struct virtio_gpu_ctrl_hdr hdr;
98 struct virtio_gpu_rect r;
Christopher Ferris05d08e92016-02-04 13:16:38 -080099 __le32 scanout_id;
100 __le32 resource_id;
101};
102struct virtio_gpu_resource_flush {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800103 struct virtio_gpu_ctrl_hdr hdr;
104 struct virtio_gpu_rect r;
105 __le32 resource_id;
106 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800107};
108struct virtio_gpu_transfer_to_host_2d {
109 struct virtio_gpu_ctrl_hdr hdr;
110 struct virtio_gpu_rect r;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800111 __le64 offset;
112 __le32 resource_id;
113 __le32 padding;
114};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800115struct virtio_gpu_mem_entry {
116 __le64 addr;
117 __le32 length;
118 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800119};
120struct virtio_gpu_resource_attach_backing {
121 struct virtio_gpu_ctrl_hdr hdr;
122 __le32 resource_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800123 __le32 nr_entries;
124};
125struct virtio_gpu_resource_detach_backing {
126 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800127 __le32 resource_id;
128 __le32 padding;
129};
130#define VIRTIO_GPU_MAX_SCANOUTS 16
Christopher Ferris05d08e92016-02-04 13:16:38 -0800131struct virtio_gpu_resp_display_info {
132 struct virtio_gpu_ctrl_hdr hdr;
133 struct virtio_gpu_display_one {
134 struct virtio_gpu_rect r;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800135 __le32 enabled;
136 __le32 flags;
137 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
138};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800139struct virtio_gpu_box {
140 __le32 x, y, z;
141 __le32 w, h, d;
142};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800143struct virtio_gpu_transfer_host_3d {
144 struct virtio_gpu_ctrl_hdr hdr;
145 struct virtio_gpu_box box;
146 __le64 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800147 __le32 resource_id;
148 __le32 level;
149 __le32 stride;
150 __le32 layer_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800151};
152#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
153struct virtio_gpu_resource_create_3d {
154 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800155 __le32 resource_id;
156 __le32 target;
157 __le32 format;
158 __le32 bind;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800159 __le32 width;
160 __le32 height;
161 __le32 depth;
162 __le32 array_size;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800163 __le32 last_level;
164 __le32 nr_samples;
165 __le32 flags;
166 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800167};
168struct virtio_gpu_ctx_create {
169 struct virtio_gpu_ctrl_hdr hdr;
170 __le32 nlen;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800171 __le32 padding;
172 char debug_name[64];
173};
174struct virtio_gpu_ctx_destroy {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800175 struct virtio_gpu_ctrl_hdr hdr;
176};
177struct virtio_gpu_ctx_resource {
178 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800179 __le32 resource_id;
180 __le32 padding;
181};
182struct virtio_gpu_cmd_submit {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800183 struct virtio_gpu_ctrl_hdr hdr;
184 __le32 size;
185 __le32 padding;
186};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800187#define VIRTIO_GPU_CAPSET_VIRGL 1
Christopher Ferris9ce28842018-10-25 12:11:39 -0700188#define VIRTIO_GPU_CAPSET_VIRGL2 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800189struct virtio_gpu_get_capset_info {
190 struct virtio_gpu_ctrl_hdr hdr;
191 __le32 capset_index;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800192 __le32 padding;
193};
194struct virtio_gpu_resp_capset_info {
195 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800196 __le32 capset_id;
197 __le32 capset_max_version;
198 __le32 capset_max_size;
199 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800200};
201struct virtio_gpu_get_capset {
202 struct virtio_gpu_ctrl_hdr hdr;
203 __le32 capset_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800204 __le32 capset_version;
205};
206struct virtio_gpu_resp_capset {
207 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700208 __u8 capset_data[];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800209};
210#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
211struct virtio_gpu_config {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800212 __u32 events_read;
213 __u32 events_clear;
214 __u32 num_scanouts;
215 __u32 num_capsets;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800216};
217enum virtio_gpu_formats {
218 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
219 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800220 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
221 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
222 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
223 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800224 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
225 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
226};
227#endif