blob: d1b6dad757b266c859dc3848126e14fd96ce993d [file] [log] [blame]
Christopher Ferrisb830ddf2024-03-28 11:48:08 -07001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
7#ifndef _UAPI_XE_DRM_H_
8#define _UAPI_XE_DRM_H_
9#include "drm.h"
10#ifdef __cplusplus
11extern "C" {
12#endif
13#define DRM_XE_DEVICE_QUERY 0x00
14#define DRM_XE_GEM_CREATE 0x01
15#define DRM_XE_GEM_MMAP_OFFSET 0x02
16#define DRM_XE_VM_CREATE 0x03
17#define DRM_XE_VM_DESTROY 0x04
18#define DRM_XE_VM_BIND 0x05
19#define DRM_XE_EXEC_QUEUE_CREATE 0x06
20#define DRM_XE_EXEC_QUEUE_DESTROY 0x07
21#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08
22#define DRM_XE_EXEC 0x09
23#define DRM_XE_WAIT_USER_FENCE 0x0a
24#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
25#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
26#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
27#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
28#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
29#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
30#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
31#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
32#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
33#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
34#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
35struct drm_xe_user_extension {
36 __u64 next_extension;
37 __u32 name;
38 __u32 pad;
39};
40struct drm_xe_ext_set_property {
41 struct drm_xe_user_extension base;
42 __u32 property;
43 __u32 pad;
44 __u64 value;
45 __u64 reserved[2];
46};
47struct drm_xe_engine_class_instance {
48#define DRM_XE_ENGINE_CLASS_RENDER 0
49#define DRM_XE_ENGINE_CLASS_COPY 1
50#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
51#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
52#define DRM_XE_ENGINE_CLASS_COMPUTE 4
53#define DRM_XE_ENGINE_CLASS_VM_BIND 5
54 __u16 engine_class;
55 __u16 engine_instance;
56 __u16 gt_id;
57 __u16 pad;
58};
59struct drm_xe_engine {
60 struct drm_xe_engine_class_instance instance;
61 __u64 reserved[3];
62};
63struct drm_xe_query_engines {
64 __u32 num_engines;
65 __u32 pad;
66 struct drm_xe_engine engines[];
67};
68enum drm_xe_memory_class {
69 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
70 DRM_XE_MEM_REGION_CLASS_VRAM
71};
72struct drm_xe_mem_region {
73 __u16 mem_class;
74 __u16 instance;
75 __u32 min_page_size;
76 __u64 total_size;
77 __u64 used;
78 __u64 cpu_visible_size;
79 __u64 cpu_visible_used;
80 __u64 reserved[6];
81};
82struct drm_xe_query_mem_regions {
83 __u32 num_mem_regions;
84 __u32 pad;
85 struct drm_xe_mem_region mem_regions[];
86};
87struct drm_xe_query_config {
88 __u32 num_params;
89 __u32 pad;
90#define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
91#define DRM_XE_QUERY_CONFIG_FLAGS 1
92#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
93#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
94#define DRM_XE_QUERY_CONFIG_VA_BITS 3
95#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
96 __u64 info[];
97};
98struct drm_xe_gt {
99#define DRM_XE_QUERY_GT_TYPE_MAIN 0
100#define DRM_XE_QUERY_GT_TYPE_MEDIA 1
101 __u16 type;
102 __u16 tile_id;
103 __u16 gt_id;
104 __u16 pad[3];
105 __u32 reference_clock;
106 __u64 near_mem_regions;
107 __u64 far_mem_regions;
Christopher Ferris7ac54f52024-08-07 21:07:12 +0000108 __u16 ip_ver_major;
109 __u16 ip_ver_minor;
110 __u16 ip_ver_rev;
111 __u16 pad2;
112 __u64 reserved[7];
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700113};
114struct drm_xe_query_gt_list {
115 __u32 num_gt;
116 __u32 pad;
117 struct drm_xe_gt gt_list[];
118};
119struct drm_xe_query_topology_mask {
120 __u16 gt_id;
Christopher Ferris7ac54f52024-08-07 21:07:12 +0000121#define DRM_XE_TOPO_DSS_GEOMETRY 1
122#define DRM_XE_TOPO_DSS_COMPUTE 2
123#define DRM_XE_TOPO_EU_PER_DSS 4
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700124 __u16 type;
125 __u32 num_bytes;
126 __u8 mask[];
127};
128struct drm_xe_query_engine_cycles {
129 struct drm_xe_engine_class_instance eci;
130 __s32 clockid;
131 __u32 width;
132 __u64 engine_cycles;
133 __u64 cpu_timestamp;
134 __u64 cpu_delta;
135};
Christopher Ferris7f4c8372024-06-03 14:22:19 -0700136struct drm_xe_query_uc_fw_version {
137#define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0
Christopher Ferris7ac54f52024-08-07 21:07:12 +0000138#define XE_QUERY_UC_TYPE_HUC 1
Christopher Ferris7f4c8372024-06-03 14:22:19 -0700139 __u16 uc_type;
140 __u16 pad;
141 __u32 branch_ver;
142 __u32 major_ver;
143 __u32 minor_ver;
144 __u32 patch_ver;
145 __u32 pad2;
146 __u64 reserved;
147};
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700148struct drm_xe_device_query {
149 __u64 extensions;
150#define DRM_XE_DEVICE_QUERY_ENGINES 0
151#define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1
152#define DRM_XE_DEVICE_QUERY_CONFIG 2
153#define DRM_XE_DEVICE_QUERY_GT_LIST 3
154#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
155#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
156#define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
Christopher Ferris7f4c8372024-06-03 14:22:19 -0700157#define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700158 __u32 query;
159 __u32 size;
160 __u64 data;
161 __u64 reserved[2];
162};
163struct drm_xe_gem_create {
164 __u64 extensions;
165 __u64 size;
166 __u32 placement;
167#define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0)
168#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1)
169#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2)
170 __u32 flags;
171 __u32 vm_id;
172 __u32 handle;
173#define DRM_XE_GEM_CPU_CACHING_WB 1
174#define DRM_XE_GEM_CPU_CACHING_WC 2
175 __u16 cpu_caching;
176 __u16 pad[3];
177 __u64 reserved[2];
178};
179struct drm_xe_gem_mmap_offset {
180 __u64 extensions;
181 __u32 handle;
182 __u32 flags;
183 __u64 offset;
184 __u64 reserved[2];
185};
186struct drm_xe_vm_create {
187 __u64 extensions;
188#define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0)
189#define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1)
190#define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2)
191 __u32 flags;
192 __u32 vm_id;
193 __u64 reserved[2];
194};
195struct drm_xe_vm_destroy {
196 __u32 vm_id;
197 __u32 pad;
198 __u64 reserved[2];
199};
200struct drm_xe_vm_bind_op {
201 __u64 extensions;
202 __u32 obj;
203 __u16 pat_index;
204 __u16 pad;
205 union {
206 __u64 obj_offset;
207 __u64 userptr;
208 };
209 __u64 range;
210 __u64 addr;
211#define DRM_XE_VM_BIND_OP_MAP 0x0
212#define DRM_XE_VM_BIND_OP_UNMAP 0x1
213#define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
214#define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
215#define DRM_XE_VM_BIND_OP_PREFETCH 0x4
216 __u32 op;
Christopher Ferris7ac54f52024-08-07 21:07:12 +0000217#define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0)
218#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1)
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700219#define DRM_XE_VM_BIND_FLAG_NULL (1 << 2)
220#define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3)
221 __u32 flags;
222 __u32 prefetch_mem_region_instance;
223 __u32 pad2;
224 __u64 reserved[3];
225};
226struct drm_xe_vm_bind {
227 __u64 extensions;
228 __u32 vm_id;
229 __u32 exec_queue_id;
230 __u32 pad;
231 __u32 num_binds;
232 union {
233 struct drm_xe_vm_bind_op bind;
234 __u64 vector_of_binds;
235 };
236 __u32 pad2;
237 __u32 num_syncs;
238 __u64 syncs;
239 __u64 reserved[2];
240};
241struct drm_xe_exec_queue_create {
242#define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
243#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
244#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
245 __u64 extensions;
246 __u16 width;
247 __u16 num_placements;
248 __u32 vm_id;
249 __u32 flags;
250 __u32 exec_queue_id;
251 __u64 instances;
252 __u64 reserved[2];
253};
254struct drm_xe_exec_queue_destroy {
255 __u32 exec_queue_id;
256 __u32 pad;
257 __u64 reserved[2];
258};
259struct drm_xe_exec_queue_get_property {
260 __u64 extensions;
261 __u32 exec_queue_id;
262#define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
263 __u32 property;
264 __u64 value;
265 __u64 reserved[2];
266};
267struct drm_xe_sync {
268 __u64 extensions;
269#define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0
270#define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1
271#define DRM_XE_SYNC_TYPE_USER_FENCE 0x2
272 __u32 type;
273#define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0)
274 __u32 flags;
275 union {
276 __u32 handle;
277 __u64 addr;
278 };
279 __u64 timeline_value;
280 __u64 reserved[2];
281};
282struct drm_xe_exec {
283 __u64 extensions;
284 __u32 exec_queue_id;
285 __u32 num_syncs;
286 __u64 syncs;
287 __u64 address;
288 __u16 num_batch_buffer;
289 __u16 pad[3];
290 __u64 reserved[2];
291};
292struct drm_xe_wait_user_fence {
293 __u64 extensions;
294 __u64 addr;
295#define DRM_XE_UFENCE_WAIT_OP_EQ 0x0
296#define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1
297#define DRM_XE_UFENCE_WAIT_OP_GT 0x2
298#define DRM_XE_UFENCE_WAIT_OP_GTE 0x3
299#define DRM_XE_UFENCE_WAIT_OP_LT 0x4
300#define DRM_XE_UFENCE_WAIT_OP_LTE 0x5
301 __u16 op;
302#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0)
303 __u16 flags;
304 __u32 pad;
305 __u64 value;
306 __u64 mask;
307 __s64 timeout;
308 __u32 exec_queue_id;
309 __u32 pad2;
310 __u64 reserved[2];
311};
312#ifdef __cplusplus
313}
314#endif
315#endif