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Christopher Ferris05d08e92016-02-04 13:16:38 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef VIRTIO_GPU_HW_H
20#define VIRTIO_GPU_HW_H
21#include <linux/types.h>
22#define VIRTIO_GPU_F_VIRGL 0
Christopher Ferrisd842e432019-03-07 10:21:59 -080023#define VIRTIO_GPU_F_EDID 1
Christopher Ferris32ff3f82020-12-14 13:10:04 -080024#define VIRTIO_GPU_F_RESOURCE_UUID 2
Christopher Ferris05667cd2021-02-16 16:01:34 -080025#define VIRTIO_GPU_F_RESOURCE_BLOB 3
Christopher Ferrisa4792612022-01-10 13:51:15 -080026#define VIRTIO_GPU_F_CONTEXT_INIT 4
Christopher Ferris05d08e92016-02-04 13:16:38 -080027enum virtio_gpu_ctrl_type {
28 VIRTIO_GPU_UNDEFINED = 0,
29 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
30 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
Christopher Ferris05d08e92016-02-04 13:16:38 -080031 VIRTIO_GPU_CMD_RESOURCE_UNREF,
32 VIRTIO_GPU_CMD_SET_SCANOUT,
33 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
34 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
Christopher Ferris05d08e92016-02-04 13:16:38 -080035 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
36 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
37 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
38 VIRTIO_GPU_CMD_GET_CAPSET,
Christopher Ferrisd842e432019-03-07 10:21:59 -080039 VIRTIO_GPU_CMD_GET_EDID,
Christopher Ferris32ff3f82020-12-14 13:10:04 -080040 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
Christopher Ferris05667cd2021-02-16 16:01:34 -080041 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
42 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
Christopher Ferris05d08e92016-02-04 13:16:38 -080043 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
44 VIRTIO_GPU_CMD_CTX_DESTROY,
45 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
46 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
Christopher Ferris05d08e92016-02-04 13:16:38 -080047 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
48 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
49 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
50 VIRTIO_GPU_CMD_SUBMIT_3D,
Christopher Ferris05667cd2021-02-16 16:01:34 -080051 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
52 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
Christopher Ferris05d08e92016-02-04 13:16:38 -080053 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
54 VIRTIO_GPU_CMD_MOVE_CURSOR,
55 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
56 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
Christopher Ferris05d08e92016-02-04 13:16:38 -080057 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
58 VIRTIO_GPU_RESP_OK_CAPSET,
Christopher Ferrisd842e432019-03-07 10:21:59 -080059 VIRTIO_GPU_RESP_OK_EDID,
Christopher Ferris32ff3f82020-12-14 13:10:04 -080060 VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
Christopher Ferris05667cd2021-02-16 16:01:34 -080061 VIRTIO_GPU_RESP_OK_MAP_INFO,
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
63 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
Christopher Ferris05d08e92016-02-04 13:16:38 -080064 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
65 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
66 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
67 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
Christopher Ferris05d08e92016-02-04 13:16:38 -080068};
Christopher Ferris05667cd2021-02-16 16:01:34 -080069enum virtio_gpu_shm_id {
70 VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
71 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
72};
Christopher Ferris05d08e92016-02-04 13:16:38 -080073#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
Christopher Ferrisa4792612022-01-10 13:51:15 -080074#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
Christopher Ferris05d08e92016-02-04 13:16:38 -080075struct virtio_gpu_ctrl_hdr {
76 __le32 type;
Christopher Ferris05d08e92016-02-04 13:16:38 -080077 __le32 flags;
78 __le64 fence_id;
79 __le32 ctx_id;
Christopher Ferrisa4792612022-01-10 13:51:15 -080080 __u8 ring_idx;
81 __u8 padding[3];
Christopher Ferris05d08e92016-02-04 13:16:38 -080082};
83struct virtio_gpu_cursor_pos {
84 __le32 scanout_id;
85 __le32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 __le32 y;
87 __le32 padding;
88};
89struct virtio_gpu_update_cursor {
Christopher Ferris05d08e92016-02-04 13:16:38 -080090 struct virtio_gpu_ctrl_hdr hdr;
91 struct virtio_gpu_cursor_pos pos;
92 __le32 resource_id;
93 __le32 hot_x;
Christopher Ferris05d08e92016-02-04 13:16:38 -080094 __le32 hot_y;
95 __le32 padding;
96};
97struct virtio_gpu_rect {
Christopher Ferris05d08e92016-02-04 13:16:38 -080098 __le32 x;
99 __le32 y;
100 __le32 width;
101 __le32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800102};
103struct virtio_gpu_resource_unref {
104 struct virtio_gpu_ctrl_hdr hdr;
105 __le32 resource_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106 __le32 padding;
107};
108struct virtio_gpu_resource_create_2d {
109 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110 __le32 resource_id;
111 __le32 format;
112 __le32 width;
113 __le32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114};
115struct virtio_gpu_set_scanout {
116 struct virtio_gpu_ctrl_hdr hdr;
117 struct virtio_gpu_rect r;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118 __le32 scanout_id;
119 __le32 resource_id;
120};
121struct virtio_gpu_resource_flush {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800122 struct virtio_gpu_ctrl_hdr hdr;
123 struct virtio_gpu_rect r;
124 __le32 resource_id;
125 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800126};
127struct virtio_gpu_transfer_to_host_2d {
128 struct virtio_gpu_ctrl_hdr hdr;
129 struct virtio_gpu_rect r;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800130 __le64 offset;
131 __le32 resource_id;
132 __le32 padding;
133};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134struct virtio_gpu_mem_entry {
135 __le64 addr;
136 __le32 length;
137 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800138};
139struct virtio_gpu_resource_attach_backing {
140 struct virtio_gpu_ctrl_hdr hdr;
141 __le32 resource_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800142 __le32 nr_entries;
143};
144struct virtio_gpu_resource_detach_backing {
145 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800146 __le32 resource_id;
147 __le32 padding;
148};
149#define VIRTIO_GPU_MAX_SCANOUTS 16
Christopher Ferris05d08e92016-02-04 13:16:38 -0800150struct virtio_gpu_resp_display_info {
151 struct virtio_gpu_ctrl_hdr hdr;
152 struct virtio_gpu_display_one {
153 struct virtio_gpu_rect r;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154 __le32 enabled;
155 __le32 flags;
156 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
157};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800158struct virtio_gpu_box {
159 __le32 x, y, z;
160 __le32 w, h, d;
161};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800162struct virtio_gpu_transfer_host_3d {
163 struct virtio_gpu_ctrl_hdr hdr;
164 struct virtio_gpu_box box;
165 __le64 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800166 __le32 resource_id;
167 __le32 level;
168 __le32 stride;
169 __le32 layer_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800170};
171#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
172struct virtio_gpu_resource_create_3d {
173 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800174 __le32 resource_id;
175 __le32 target;
176 __le32 format;
177 __le32 bind;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800178 __le32 width;
179 __le32 height;
180 __le32 depth;
181 __le32 array_size;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800182 __le32 last_level;
183 __le32 nr_samples;
184 __le32 flags;
185 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800186};
Christopher Ferrisa4792612022-01-10 13:51:15 -0800187#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
Christopher Ferris05d08e92016-02-04 13:16:38 -0800188struct virtio_gpu_ctx_create {
189 struct virtio_gpu_ctrl_hdr hdr;
190 __le32 nlen;
Christopher Ferrisa4792612022-01-10 13:51:15 -0800191 __le32 context_init;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800192 char debug_name[64];
193};
194struct virtio_gpu_ctx_destroy {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800195 struct virtio_gpu_ctrl_hdr hdr;
196};
197struct virtio_gpu_ctx_resource {
198 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800199 __le32 resource_id;
200 __le32 padding;
201};
202struct virtio_gpu_cmd_submit {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800203 struct virtio_gpu_ctrl_hdr hdr;
204 __le32 size;
205 __le32 padding;
206};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800207#define VIRTIO_GPU_CAPSET_VIRGL 1
Christopher Ferris9ce28842018-10-25 12:11:39 -0700208#define VIRTIO_GPU_CAPSET_VIRGL2 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800209struct virtio_gpu_get_capset_info {
210 struct virtio_gpu_ctrl_hdr hdr;
211 __le32 capset_index;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800212 __le32 padding;
213};
214struct virtio_gpu_resp_capset_info {
215 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800216 __le32 capset_id;
217 __le32 capset_max_version;
218 __le32 capset_max_size;
219 __le32 padding;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800220};
221struct virtio_gpu_get_capset {
222 struct virtio_gpu_ctrl_hdr hdr;
223 __le32 capset_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800224 __le32 capset_version;
225};
226struct virtio_gpu_resp_capset {
227 struct virtio_gpu_ctrl_hdr hdr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700228 __u8 capset_data[];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800229};
Christopher Ferrisd842e432019-03-07 10:21:59 -0800230struct virtio_gpu_cmd_get_edid {
231 struct virtio_gpu_ctrl_hdr hdr;
232 __le32 scanout;
233 __le32 padding;
234};
235struct virtio_gpu_resp_edid {
236 struct virtio_gpu_ctrl_hdr hdr;
237 __le32 size;
238 __le32 padding;
239 __u8 edid[1024];
240};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800241#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
242struct virtio_gpu_config {
Christopher Ferris25c18d42020-10-14 17:42:58 -0700243 __le32 events_read;
244 __le32 events_clear;
245 __le32 num_scanouts;
246 __le32 num_capsets;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800247};
248enum virtio_gpu_formats {
249 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
250 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800251 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
252 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
253 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
254 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800255 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
256 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
257};
Christopher Ferris32ff3f82020-12-14 13:10:04 -0800258struct virtio_gpu_resource_assign_uuid {
259 struct virtio_gpu_ctrl_hdr hdr;
260 __le32 resource_id;
261 __le32 padding;
262};
263struct virtio_gpu_resp_resource_uuid {
264 struct virtio_gpu_ctrl_hdr hdr;
265 __u8 uuid[16];
266};
Christopher Ferris05667cd2021-02-16 16:01:34 -0800267struct virtio_gpu_resource_create_blob {
268 struct virtio_gpu_ctrl_hdr hdr;
269 __le32 resource_id;
270#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
271#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
272#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
273#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
274#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
275#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
276 __le32 blob_mem;
277 __le32 blob_flags;
278 __le32 nr_entries;
279 __le64 blob_id;
280 __le64 size;
281};
282struct virtio_gpu_set_scanout_blob {
283 struct virtio_gpu_ctrl_hdr hdr;
284 struct virtio_gpu_rect r;
285 __le32 scanout_id;
286 __le32 resource_id;
287 __le32 width;
288 __le32 height;
289 __le32 format;
290 __le32 padding;
291 __le32 strides[4];
292 __le32 offsets[4];
293};
294struct virtio_gpu_resource_map_blob {
295 struct virtio_gpu_ctrl_hdr hdr;
296 __le32 resource_id;
297 __le32 padding;
298 __le64 offset;
299};
300#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
301#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
302#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
303#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
304#define VIRTIO_GPU_MAP_CACHE_WC 0x03
305struct virtio_gpu_resp_map_info {
306 struct virtio_gpu_ctrl_hdr hdr;
307 __u32 map_info;
308 __u32 padding;
309};
310struct virtio_gpu_resource_unmap_blob {
311 struct virtio_gpu_ctrl_hdr hdr;
312 __le32 resource_id;
313 __le32 padding;
314};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800315#endif