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gerrit.omnirom.org / android_bionic / bc65c019404b2f9b5a6894e42a30f1c398d6da99 / . / libc / kernel / uapi / linux / isst_if.h
blob: 8d0b64a3e5d6f4eedabcb05e26031415c1e7ee81 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame]7#ifndef __ISST_IF_H
8#define __ISST_IF_H
9#include <linux/types.h>
10struct isst_if_platform_info {
11 __u16 api_version;
12 __u16 driver_version;
13 __u16 max_cmds_per_ioctl;
14 __u8 mbox_supported;
15 __u8 mmio_supported;
16};
17struct isst_if_cpu_map {
18 __u32 logical_cpu;
19 __u32 physical_cpu;
20};
21struct isst_if_cpu_maps {
22 __u32 cmd_count;
23 struct isst_if_cpu_map cpu_map[1];
24};
25struct isst_if_io_reg {
26 __u32 read_write;
27 __u32 logical_cpu;
28 __u32 reg;
29 __u32 value;
30};
31struct isst_if_io_regs {
32 __u32 req_count;
33 struct isst_if_io_reg io_reg[1];
34};
35struct isst_if_mbox_cmd {
36 __u32 logical_cpu;
37 __u32 parameter;
38 __u32 req_data;
39 __u32 resp_data;
40 __u16 command;
41 __u16 sub_command;
42 __u32 reserved;
43};
44struct isst_if_mbox_cmds {
45 __u32 cmd_count;
46 struct isst_if_mbox_cmd mbox_cmd[1];
47};
48struct isst_if_msr_cmd {
49 __u32 read_write;
50 __u32 logical_cpu;
51 __u64 msr;
52 __u64 data;
53};
54struct isst_if_msr_cmds {
55 __u32 cmd_count;
56 struct isst_if_msr_cmd msr_cmd[1];
57};
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700[diff] [blame]58struct isst_core_power {
59 __u8 get_set;
60 __u8 socket_id;
61 __u8 power_domain_id;
62 __u8 enable;
63 __u8 supported;
64 __u8 priority_type;
65};
66struct isst_clos_param {
67 __u8 get_set;
68 __u8 socket_id;
69 __u8 power_domain_id;
70 __u8 clos;
71 __u16 min_freq_mhz;
72 __u16 max_freq_mhz;
73 __u8 prop_prio;
74};
75struct isst_if_clos_assoc {
76 __u8 socket_id;
77 __u8 power_domain_id;
78 __u16 logical_cpu;
79 __u16 clos;
80};
81struct isst_if_clos_assoc_cmds {
82 __u16 cmd_count;
83 __u16 get_set;
84 __u16 punit_cpu_map;
85 struct isst_if_clos_assoc assoc_info[1];
86};
87struct isst_tpmi_instance_count {
88 __u8 socket_id;
89 __u8 count;
90 __u16 valid_mask;
91};
92struct isst_perf_level_info {
93 __u8 socket_id;
94 __u8 power_domain_id;
95 __u8 max_level;
96 __u8 feature_rev;
97 __u8 level_mask;
98 __u8 current_level;
99 __u8 feature_state;
100 __u8 locked;
101 __u8 enabled;
102 __u8 sst_tf_support;
103 __u8 sst_bf_support;
104};
105struct isst_perf_level_control {
106 __u8 socket_id;
107 __u8 power_domain_id;
108 __u8 level;
109};
110struct isst_perf_feature_control {
111 __u8 socket_id;
112 __u8 power_domain_id;
113 __u8 feature;
114};
115#define TRL_MAX_BUCKETS 8
116#define TRL_MAX_LEVELS 6
117struct isst_perf_level_data_info {
118 __u8 socket_id;
119 __u8 power_domain_id;
120 __u16 level;
121 __u16 tdp_ratio;
122 __u16 base_freq_mhz;
123 __u16 base_freq_avx2_mhz;
124 __u16 base_freq_avx512_mhz;
125 __u16 base_freq_amx_mhz;
126 __u16 thermal_design_power_w;
127 __u16 tjunction_max_c;
128 __u16 max_memory_freq_mhz;
129 __u16 cooling_type;
130 __u16 p0_freq_mhz;
131 __u16 p1_freq_mhz;
132 __u16 pn_freq_mhz;
133 __u16 pm_freq_mhz;
134 __u16 p0_fabric_freq_mhz;
135 __u16 p1_fabric_freq_mhz;
136 __u16 pn_fabric_freq_mhz;
137 __u16 pm_fabric_freq_mhz;
138 __u16 max_buckets;
139 __u16 max_trl_levels;
140 __u16 bucket_core_counts[TRL_MAX_BUCKETS];
141 __u16 trl_freq_mhz[TRL_MAX_LEVELS][TRL_MAX_BUCKETS];
142};
143struct isst_perf_level_cpu_mask {
144 __u8 socket_id;
145 __u8 power_domain_id;
146 __u8 level;
147 __u8 punit_cpu_map;
148 __u64 mask;
149 __u16 cpu_buffer_size;
150 __s8 cpu_buffer[1];
151};
152struct isst_base_freq_info {
153 __u8 socket_id;
154 __u8 power_domain_id;
155 __u16 level;
156 __u16 high_base_freq_mhz;
157 __u16 low_base_freq_mhz;
158 __u16 tjunction_max_c;
159 __u16 thermal_design_power_w;
160};
161struct isst_turbo_freq_info {
162 __u8 socket_id;
163 __u8 power_domain_id;
164 __u16 level;
165 __u16 max_clip_freqs;
166 __u16 max_buckets;
167 __u16 max_trl_levels;
168 __u16 lp_clip_freq_mhz[TRL_MAX_LEVELS];
169 __u16 bucket_core_counts[TRL_MAX_BUCKETS];
170 __u16 trl_freq_mhz[TRL_MAX_LEVELS][TRL_MAX_BUCKETS];
171};
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame]172#define ISST_IF_MAGIC 0xFE
173#define ISST_IF_GET_PLATFORM_INFO _IOR(ISST_IF_MAGIC, 0, struct isst_if_platform_info *)
174#define ISST_IF_GET_PHY_ID _IOWR(ISST_IF_MAGIC, 1, struct isst_if_cpu_map *)
175#define ISST_IF_IO_CMD _IOW(ISST_IF_MAGIC, 2, struct isst_if_io_regs *)
176#define ISST_IF_MBOX_COMMAND _IOWR(ISST_IF_MAGIC, 3, struct isst_if_mbox_cmds *)
177#define ISST_IF_MSR_COMMAND _IOWR(ISST_IF_MAGIC, 4, struct isst_if_msr_cmds *)
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700[diff] [blame]178#define ISST_IF_COUNT_TPMI_INSTANCES _IOR(ISST_IF_MAGIC, 5, struct isst_tpmi_instance_count *)
179#define ISST_IF_CORE_POWER_STATE _IOWR(ISST_IF_MAGIC, 6, struct isst_core_power *)
180#define ISST_IF_CLOS_PARAM _IOWR(ISST_IF_MAGIC, 7, struct isst_clos_param *)
181#define ISST_IF_CLOS_ASSOC _IOWR(ISST_IF_MAGIC, 8, struct isst_if_clos_assoc_cmds *)
182#define ISST_IF_PERF_LEVELS _IOWR(ISST_IF_MAGIC, 9, struct isst_perf_level_info *)
183#define ISST_IF_PERF_SET_LEVEL _IOW(ISST_IF_MAGIC, 10, struct isst_perf_level_control *)
184#define ISST_IF_PERF_SET_FEATURE _IOW(ISST_IF_MAGIC, 11, struct isst_perf_feature_control *)
185#define ISST_IF_GET_PERF_LEVEL_INFO _IOR(ISST_IF_MAGIC, 12, struct isst_perf_level_data_info *)
186#define ISST_IF_GET_PERF_LEVEL_CPU_MASK _IOR(ISST_IF_MAGIC, 13, struct isst_perf_level_cpu_mask *)
187#define ISST_IF_GET_BASE_FREQ_INFO _IOR(ISST_IF_MAGIC, 14, struct isst_base_freq_info *)
188#define ISST_IF_GET_BASE_FREQ_CPU_MASK _IOR(ISST_IF_MAGIC, 15, struct isst_perf_level_cpu_mask *)
189#define ISST_IF_GET_TURBO_FREQ_INFO _IOR(ISST_IF_MAGIC, 16, struct isst_turbo_freq_info *)
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame]190#endif