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Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef _UAPI_HDLCDRV_H
8#define _UAPI_HDLCDRV_H
9struct hdlcdrv_params {
Tao Baod7db5942015-01-28 10:07:51 -080010 int iobase;
Tao Baod7db5942015-01-28 10:07:51 -080011 int irq;
12 int dma;
13 int dma2;
14 int seriobase;
Tao Baod7db5942015-01-28 10:07:51 -080015 int pariobase;
16 int midiiobase;
Ben Cheng655a7c02013-10-16 16:09:24 -070017};
18struct hdlcdrv_channel_params {
Tao Baod7db5942015-01-28 10:07:51 -080019 int tx_delay;
20 int tx_tail;
21 int slottime;
22 int ppersist;
Tao Baod7db5942015-01-28 10:07:51 -080023 int fulldup;
Ben Cheng655a7c02013-10-16 16:09:24 -070024};
25struct hdlcdrv_old_channel_state {
Tao Baod7db5942015-01-28 10:07:51 -080026 int ptt;
Tao Baod7db5942015-01-28 10:07:51 -080027 int dcd;
28 int ptt_keyed;
Ben Cheng655a7c02013-10-16 16:09:24 -070029};
30struct hdlcdrv_channel_state {
Tao Baod7db5942015-01-28 10:07:51 -080031 int ptt;
32 int dcd;
33 int ptt_keyed;
34 unsigned long tx_packets;
Tao Baod7db5942015-01-28 10:07:51 -080035 unsigned long tx_errors;
36 unsigned long rx_packets;
37 unsigned long rx_errors;
Ben Cheng655a7c02013-10-16 16:09:24 -070038};
Ben Cheng655a7c02013-10-16 16:09:24 -070039struct hdlcdrv_ioctl {
Tao Baod7db5942015-01-28 10:07:51 -080040 int cmd;
41 union {
42 struct hdlcdrv_params mp;
Tao Baod7db5942015-01-28 10:07:51 -080043 struct hdlcdrv_channel_params cp;
44 struct hdlcdrv_channel_state cs;
45 struct hdlcdrv_old_channel_state ocs;
46 unsigned int calibrate;
Tao Baod7db5942015-01-28 10:07:51 -080047 unsigned char bits;
48 char modename[128];
49 char drivername[32];
50 } data;
Ben Cheng655a7c02013-10-16 16:09:24 -070051};
52#define HDLCDRVCTL_GETMODEMPAR 0
53#define HDLCDRVCTL_SETMODEMPAR 1
54#define HDLCDRVCTL_MODEMPARMASK 2
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define HDLCDRVCTL_GETCHANNELPAR 10
56#define HDLCDRVCTL_SETCHANNELPAR 11
57#define HDLCDRVCTL_OLDGETSTAT 20
58#define HDLCDRVCTL_CALIBRATE 21
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define HDLCDRVCTL_GETSTAT 22
60#define HDLCDRVCTL_GETSAMPLES 30
61#define HDLCDRVCTL_GETBITS 31
62#define HDLCDRVCTL_GETMODE 40
Ben Cheng655a7c02013-10-16 16:09:24 -070063#define HDLCDRVCTL_SETMODE 41
64#define HDLCDRVCTL_MODELIST 42
65#define HDLCDRVCTL_DRIVERNAME 43
Tao Baod7db5942015-01-28 10:07:51 -080066#define HDLCDRV_PARMASK_IOBASE (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -080067#define HDLCDRV_PARMASK_IRQ (1 << 1)
68#define HDLCDRV_PARMASK_DMA (1 << 2)
69#define HDLCDRV_PARMASK_DMA2 (1 << 3)
70#define HDLCDRV_PARMASK_SERIOBASE (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -080071#define HDLCDRV_PARMASK_PARIOBASE (1 << 5)
72#define HDLCDRV_PARMASK_MIDIIOBASE (1 << 6)
Ben Cheng655a7c02013-10-16 16:09:24 -070073#endif