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gerrit.omnirom.org / android_bionic / bb9fcb46361ddb55aac7faf639de5088a09b9b8e / . / libc / kernel / uapi / linux / idxd.h
blob: 9c96af8ed6cdb1de3bbd38095bf6a7ff647b0812 [file] [log] [blame]
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700[diff] [blame^]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _USR_IDXD_H_
20#define _USR_IDXD_H_
21#include <stdint.h>
22#define IDXD_OP_FLAG_FENCE 0x0001
23#define IDXD_OP_FLAG_BOF 0x0002
24#define IDXD_OP_FLAG_CRAV 0x0004
25#define IDXD_OP_FLAG_RCR 0x0008
26#define IDXD_OP_FLAG_RCI 0x0010
27#define IDXD_OP_FLAG_CRSTS 0x0020
28#define IDXD_OP_FLAG_CR 0x0080
29#define IDXD_OP_FLAG_CC 0x0100
30#define IDXD_OP_FLAG_ADDR1_TCS 0x0200
31#define IDXD_OP_FLAG_ADDR2_TCS 0x0400
32#define IDXD_OP_FLAG_ADDR3_TCS 0x0800
33#define IDXD_OP_FLAG_CR_TCS 0x1000
34#define IDXD_OP_FLAG_STORD 0x2000
35#define IDXD_OP_FLAG_DRDBK 0x4000
36#define IDXD_OP_FLAG_DSTS 0x8000
37enum dsa_opcode {
38 DSA_OPCODE_NOOP = 0,
39 DSA_OPCODE_BATCH,
40 DSA_OPCODE_DRAIN,
41 DSA_OPCODE_MEMMOVE,
42 DSA_OPCODE_MEMFILL,
43 DSA_OPCODE_COMPARE,
44 DSA_OPCODE_COMPVAL,
45 DSA_OPCODE_CR_DELTA,
46 DSA_OPCODE_AP_DELTA,
47 DSA_OPCODE_DUALCAST,
48 DSA_OPCODE_CRCGEN = 0x10,
49 DSA_OPCODE_COPY_CRC,
50 DSA_OPCODE_DIF_CHECK,
51 DSA_OPCODE_DIF_INS,
52 DSA_OPCODE_DIF_STRP,
53 DSA_OPCODE_DIF_UPDT,
54 DSA_OPCODE_CFLUSH = 0x20,
55};
56enum dsa_completion_status {
57 DSA_COMP_NONE = 0,
58 DSA_COMP_SUCCESS,
59 DSA_COMP_SUCCESS_PRED,
60 DSA_COMP_PAGE_FAULT_NOBOF,
61 DSA_COMP_PAGE_FAULT_IR,
62 DSA_COMP_BATCH_FAIL,
63 DSA_COMP_BATCH_PAGE_FAULT,
64 DSA_COMP_DR_OFFSET_NOINC,
65 DSA_COMP_DR_OFFSET_ERANGE,
66 DSA_COMP_DIF_ERR,
67 DSA_COMP_BAD_OPCODE = 0x10,
68 DSA_COMP_INVALID_FLAGS,
69 DSA_COMP_NOZERO_RESERVE,
70 DSA_COMP_XFER_ERANGE,
71 DSA_COMP_DESC_CNT_ERANGE,
72 DSA_COMP_DR_ERANGE,
73 DSA_COMP_OVERLAP_BUFFERS,
74 DSA_COMP_DCAST_ERR,
75 DSA_COMP_DESCLIST_ALIGN,
76 DSA_COMP_INT_HANDLE_INVAL,
77 DSA_COMP_CRA_XLAT,
78 DSA_COMP_CRA_ALIGN,
79 DSA_COMP_ADDR_ALIGN,
80 DSA_COMP_PRIV_BAD,
81 DSA_COMP_TRAFFIC_CLASS_CONF,
82 DSA_COMP_PFAULT_RDBA,
83 DSA_COMP_HW_ERR1,
84 DSA_COMP_HW_ERR_DRB,
85 DSA_COMP_TRANSLATION_FAIL,
86};
87#define DSA_COMP_STATUS_MASK 0x7f
88#define DSA_COMP_STATUS_WRITE 0x80
89struct dsa_batch_desc {
90 uint32_t pasid : 20;
91 uint32_t rsvd : 11;
92 uint32_t priv : 1;
93 uint32_t flags : 24;
94 uint32_t opcode : 8;
95 uint64_t completion_addr;
96 uint64_t desc_list_addr;
97 uint64_t rsvd1;
98 uint32_t desc_count;
99 uint16_t interrupt_handle;
100 uint16_t rsvd2;
101 uint8_t rsvd3[24];
102} __attribute__((packed));
103struct dsa_hw_desc {
104 uint32_t pasid : 20;
105 uint32_t rsvd : 11;
106 uint32_t priv : 1;
107 uint32_t flags : 24;
108 uint32_t opcode : 8;
109 uint64_t completion_addr;
110 union {
111 uint64_t src_addr;
112 uint64_t rdback_addr;
113 uint64_t pattern;
114 };
115 union {
116 uint64_t dst_addr;
117 uint64_t rdback_addr2;
118 uint64_t src2_addr;
119 uint64_t comp_pattern;
120 };
121 uint32_t xfer_size;
122 uint16_t int_handle;
123 uint16_t rsvd1;
124 union {
125 uint8_t expected_res;
126 struct {
127 uint64_t delta_addr;
128 uint32_t max_delta_size;
129 };
130 uint32_t delta_rec_size;
131 uint64_t dest2;
132 struct {
133 uint32_t crc_seed;
134 uint32_t crc_rsvd;
135 uint64_t seed_addr;
136 };
137 struct {
138 uint8_t src_dif_flags;
139 uint8_t dif_chk_res;
140 uint8_t dif_chk_flags;
141 uint8_t dif_chk_res2[5];
142 uint32_t chk_ref_tag_seed;
143 uint16_t chk_app_tag_mask;
144 uint16_t chk_app_tag_seed;
145 };
146 struct {
147 uint8_t dif_ins_res;
148 uint8_t dest_dif_flag;
149 uint8_t dif_ins_flags;
150 uint8_t dif_ins_res2[13];
151 uint32_t ins_ref_tag_seed;
152 uint16_t ins_app_tag_mask;
153 uint16_t ins_app_tag_seed;
154 };
155 struct {
156 uint8_t src_upd_flags;
157 uint8_t upd_dest_flags;
158 uint8_t dif_upd_flags;
159 uint8_t dif_upd_res[5];
160 uint32_t src_ref_tag_seed;
161 uint16_t src_app_tag_mask;
162 uint16_t src_app_tag_seed;
163 uint32_t dest_ref_tag_seed;
164 uint16_t dest_app_tag_mask;
165 uint16_t dest_app_tag_seed;
166 };
167 uint8_t op_specific[24];
168 };
169} __attribute__((packed));
170struct dsa_raw_desc {
171 uint64_t field[8];
172} __attribute__((packed));
173struct dsa_completion_record {
174 volatile uint8_t status;
175 union {
176 uint8_t result;
177 uint8_t dif_status;
178 };
179 uint16_t rsvd;
180 uint32_t bytes_completed;
181 uint64_t fault_addr;
182 union {
183 uint16_t delta_rec_size;
184 uint16_t crc_val;
185 struct {
186 uint32_t dif_chk_ref_tag;
187 uint16_t dif_chk_app_tag_mask;
188 uint16_t dif_chk_app_tag;
189 };
190 struct {
191 uint64_t dif_ins_res;
192 uint32_t dif_ins_ref_tag;
193 uint16_t dif_ins_app_tag_mask;
194 uint16_t dif_ins_app_tag;
195 };
196 struct {
197 uint32_t dif_upd_src_ref_tag;
198 uint16_t dif_upd_src_app_tag_mask;
199 uint16_t dif_upd_src_app_tag;
200 uint32_t dif_upd_dest_ref_tag;
201 uint16_t dif_upd_dest_app_tag_mask;
202 uint16_t dif_upd_dest_app_tag;
203 };
204 uint8_t op_specific[16];
205 };
206} __attribute__((packed));
207struct dsa_raw_completion_record {
208 uint64_t field[4];
209} __attribute__((packed));
210#endif