Elliott Hughes | 180edef | 2023-11-02 00:08:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is auto-generated. Modifications will be lost. |
| 3 | * |
| 4 | * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ |
| 5 | * for more information. |
| 6 | */ |
Christopher Ferris | 80ae69d | 2022-08-02 16:32:21 -0700 | [diff] [blame] | 7 | #ifndef SCSI_BSG_MPI3MR_H_INCLUDED |
| 8 | #define SCSI_BSG_MPI3MR_H_INCLUDED |
| 9 | #include <linux/types.h> |
| 10 | #define MPI3MR_IOCTL_VERSION 0x06 |
| 11 | #define MPI3MR_APP_DEFAULT_TIMEOUT (60) |
| 12 | #define MPI3MR_BSG_ADPTYPE_UNKNOWN 0 |
| 13 | #define MPI3MR_BSG_ADPTYPE_AVGFAMILY 1 |
| 14 | #define MPI3MR_BSG_ADPSTATE_UNKNOWN 0 |
| 15 | #define MPI3MR_BSG_ADPSTATE_OPERATIONAL 1 |
| 16 | #define MPI3MR_BSG_ADPSTATE_FAULT 2 |
| 17 | #define MPI3MR_BSG_ADPSTATE_IN_RESET 3 |
| 18 | #define MPI3MR_BSG_ADPSTATE_UNRECOVERABLE 4 |
| 19 | #define MPI3MR_BSG_ADPRESET_UNKNOWN 0 |
| 20 | #define MPI3MR_BSG_ADPRESET_SOFT 1 |
| 21 | #define MPI3MR_BSG_ADPRESET_DIAG_FAULT 2 |
| 22 | #define MPI3MR_BSG_LOGDATA_MAX_ENTRIES 400 |
| 23 | #define MPI3MR_BSG_LOGDATA_ENTRY_HEADER_SZ 4 |
| 24 | #define MPI3MR_DRVBSG_OPCODE_UNKNOWN 0 |
| 25 | #define MPI3MR_DRVBSG_OPCODE_ADPINFO 1 |
| 26 | #define MPI3MR_DRVBSG_OPCODE_ADPRESET 2 |
| 27 | #define MPI3MR_DRVBSG_OPCODE_ALLTGTDEVINFO 4 |
| 28 | #define MPI3MR_DRVBSG_OPCODE_GETCHGCNT 5 |
| 29 | #define MPI3MR_DRVBSG_OPCODE_LOGDATAENABLE 6 |
| 30 | #define MPI3MR_DRVBSG_OPCODE_PELENABLE 7 |
| 31 | #define MPI3MR_DRVBSG_OPCODE_GETLOGDATA 8 |
| 32 | #define MPI3MR_DRVBSG_OPCODE_QUERY_HDB 9 |
| 33 | #define MPI3MR_DRVBSG_OPCODE_REPOST_HDB 10 |
| 34 | #define MPI3MR_DRVBSG_OPCODE_UPLOAD_HDB 11 |
| 35 | #define MPI3MR_DRVBSG_OPCODE_REFRESH_HDB_TRIGGERS 12 |
| 36 | #define MPI3MR_BSG_BUFTYPE_UNKNOWN 0 |
| 37 | #define MPI3MR_BSG_BUFTYPE_RAIDMGMT_CMD 1 |
| 38 | #define MPI3MR_BSG_BUFTYPE_RAIDMGMT_RESP 2 |
| 39 | #define MPI3MR_BSG_BUFTYPE_DATA_IN 3 |
| 40 | #define MPI3MR_BSG_BUFTYPE_DATA_OUT 4 |
| 41 | #define MPI3MR_BSG_BUFTYPE_MPI_REPLY 5 |
| 42 | #define MPI3MR_BSG_BUFTYPE_ERR_RESPONSE 6 |
| 43 | #define MPI3MR_BSG_BUFTYPE_MPI_REQUEST 0xFE |
| 44 | #define MPI3MR_BSG_MPI_REPLY_BUFTYPE_UNKNOWN 0 |
| 45 | #define MPI3MR_BSG_MPI_REPLY_BUFTYPE_STATUS 1 |
| 46 | #define MPI3MR_BSG_MPI_REPLY_BUFTYPE_ADDRESS 2 |
| 47 | #define MPI3MR_HDB_BUFTYPE_UNKNOWN 0 |
| 48 | #define MPI3MR_HDB_BUFTYPE_TRACE 1 |
| 49 | #define MPI3MR_HDB_BUFTYPE_FIRMWARE 2 |
| 50 | #define MPI3MR_HDB_BUFTYPE_RESERVED 3 |
| 51 | #define MPI3MR_HDB_BUFSTATUS_UNKNOWN 0 |
| 52 | #define MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED 1 |
| 53 | #define MPI3MR_HDB_BUFSTATUS_POSTED_UNPAUSED 2 |
| 54 | #define MPI3MR_HDB_BUFSTATUS_POSTED_PAUSED 3 |
| 55 | #define MPI3MR_HDB_BUFSTATUS_RELEASED 4 |
| 56 | #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0 |
| 57 | #define MPI3MR_HDB_TRIGGER_TYPE_DIAGFAULT 1 |
| 58 | #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2 |
| 59 | #define MPI3MR_HDB_TRIGGER_TYPE_MASTER 3 |
| 60 | enum command { |
| 61 | MPI3MR_DRV_CMD = 1, |
| 62 | MPI3MR_MPT_CMD = 2, |
| 63 | }; |
| 64 | struct mpi3_driver_info_layout { |
| 65 | __le32 information_length; |
| 66 | __u8 driver_signature[12]; |
| 67 | __u8 os_name[16]; |
| 68 | __u8 os_version[12]; |
| 69 | __u8 driver_name[20]; |
| 70 | __u8 driver_version[32]; |
| 71 | __u8 driver_release_date[20]; |
| 72 | __le32 driver_capabilities; |
| 73 | }; |
| 74 | struct mpi3mr_bsg_in_adpinfo { |
| 75 | __u32 adp_type; |
| 76 | __u32 rsvd1; |
| 77 | __u32 pci_dev_id; |
| 78 | __u32 pci_dev_hw_rev; |
| 79 | __u32 pci_subsys_dev_id; |
| 80 | __u32 pci_subsys_ven_id; |
| 81 | __u32 pci_dev : 5; |
| 82 | __u32 pci_func : 3; |
| 83 | __u32 pci_bus : 8; |
| 84 | __u16 rsvd2; |
| 85 | __u32 pci_seg_id; |
| 86 | __u32 app_intfc_ver; |
| 87 | __u8 adp_state; |
| 88 | __u8 rsvd3; |
| 89 | __u16 rsvd4; |
| 90 | __u32 rsvd5[2]; |
| 91 | struct mpi3_driver_info_layout driver_info; |
| 92 | }; |
| 93 | struct mpi3mr_bsg_adp_reset { |
| 94 | __u8 reset_type; |
| 95 | __u8 rsvd1; |
| 96 | __u16 rsvd2; |
| 97 | }; |
| 98 | struct mpi3mr_change_count { |
| 99 | __u16 change_count; |
| 100 | __u16 rsvd; |
| 101 | }; |
| 102 | struct mpi3mr_device_map_info { |
| 103 | __u16 handle; |
| 104 | __u16 perst_id; |
| 105 | __u32 target_id; |
| 106 | __u8 bus_id; |
| 107 | __u8 rsvd1; |
| 108 | __u16 rsvd2; |
| 109 | }; |
| 110 | struct mpi3mr_all_tgt_info { |
| 111 | __u16 num_devices; |
| 112 | __u16 rsvd1; |
| 113 | __u32 rsvd2; |
| 114 | struct mpi3mr_device_map_info dmi[1]; |
| 115 | }; |
| 116 | struct mpi3mr_logdata_enable { |
| 117 | __u16 max_entries; |
| 118 | __u16 rsvd; |
| 119 | }; |
| 120 | struct mpi3mr_bsg_out_pel_enable { |
| 121 | __u16 pel_locale; |
| 122 | __u8 pel_class; |
| 123 | __u8 rsvd; |
| 124 | }; |
| 125 | struct mpi3mr_logdata_entry { |
| 126 | __u8 valid_entry; |
| 127 | __u8 rsvd1; |
| 128 | __u16 rsvd2; |
| 129 | __u8 data[1]; |
| 130 | }; |
| 131 | struct mpi3mr_bsg_in_log_data { |
| 132 | struct mpi3mr_logdata_entry entry[1]; |
| 133 | }; |
| 134 | struct mpi3mr_hdb_entry { |
| 135 | __u8 buf_type; |
| 136 | __u8 status; |
| 137 | __u8 trigger_type; |
| 138 | __u8 rsvd1; |
| 139 | __u16 size; |
| 140 | __u16 rsvd2; |
| 141 | __u64 trigger_data; |
| 142 | __u32 rsvd3; |
| 143 | __u32 rsvd4; |
| 144 | }; |
| 145 | struct mpi3mr_bsg_in_hdb_status { |
| 146 | __u8 num_hdb_types; |
| 147 | __u8 rsvd1; |
| 148 | __u16 rsvd2; |
| 149 | __u32 rsvd3; |
| 150 | struct mpi3mr_hdb_entry entry[1]; |
| 151 | }; |
| 152 | struct mpi3mr_bsg_out_repost_hdb { |
| 153 | __u8 buf_type; |
| 154 | __u8 rsvd1; |
| 155 | __u16 rsvd2; |
| 156 | }; |
| 157 | struct mpi3mr_bsg_out_upload_hdb { |
| 158 | __u8 buf_type; |
| 159 | __u8 rsvd1; |
| 160 | __u16 rsvd2; |
| 161 | __u32 start_offset; |
| 162 | __u32 length; |
| 163 | }; |
| 164 | struct mpi3mr_bsg_out_refresh_hdb_triggers { |
| 165 | __u8 page_type; |
| 166 | __u8 rsvd1; |
| 167 | __u16 rsvd2; |
| 168 | }; |
| 169 | struct mpi3mr_bsg_drv_cmd { |
| 170 | __u8 mrioc_id; |
| 171 | __u8 opcode; |
| 172 | __u16 rsvd1; |
| 173 | __u32 rsvd2[4]; |
| 174 | }; |
| 175 | struct mpi3mr_bsg_in_reply_buf { |
| 176 | __u8 mpi_reply_type; |
| 177 | __u8 rsvd1; |
| 178 | __u16 rsvd2; |
| 179 | __u8 reply_buf[1]; |
| 180 | }; |
| 181 | struct mpi3mr_buf_entry { |
| 182 | __u8 buf_type; |
| 183 | __u8 rsvd1; |
| 184 | __u16 rsvd2; |
| 185 | __u32 buf_len; |
| 186 | }; |
| 187 | struct mpi3mr_buf_entry_list { |
| 188 | __u8 num_of_entries; |
| 189 | __u8 rsvd1; |
| 190 | __u16 rsvd2; |
| 191 | __u32 rsvd3; |
| 192 | struct mpi3mr_buf_entry buf_entry[1]; |
| 193 | }; |
| 194 | struct mpi3mr_bsg_mptcmd { |
| 195 | __u8 mrioc_id; |
| 196 | __u8 rsvd1; |
| 197 | __u16 timeout; |
| 198 | __u32 rsvd2; |
| 199 | struct mpi3mr_buf_entry_list buf_entry_list; |
| 200 | }; |
| 201 | struct mpi3mr_bsg_packet { |
| 202 | __u8 cmd_type; |
| 203 | __u8 rsvd1; |
| 204 | __u16 rsvd2; |
| 205 | __u32 rsvd3; |
| 206 | union { |
| 207 | struct mpi3mr_bsg_drv_cmd drvrcmd; |
| 208 | struct mpi3mr_bsg_mptcmd mptcmd; |
| 209 | } cmd; |
| 210 | }; |
Christopher Ferris | 80ae69d | 2022-08-02 16:32:21 -0700 | [diff] [blame] | 211 | struct mpi3_nvme_encapsulated_request { |
| 212 | __le16 host_tag; |
| 213 | __u8 ioc_use_only02; |
| 214 | __u8 function; |
| 215 | __le16 ioc_use_only04; |
| 216 | __u8 ioc_use_only06; |
| 217 | __u8 msg_flags; |
| 218 | __le16 change_count; |
| 219 | __le16 dev_handle; |
| 220 | __le16 encapsulated_command_length; |
| 221 | __le16 flags; |
| 222 | __le32 data_length; |
| 223 | __le32 reserved14[3]; |
Christopher Ferris | b7cef6d | 2023-05-09 19:04:15 +0000 | [diff] [blame] | 224 | __le32 command[]; |
Christopher Ferris | 80ae69d | 2022-08-02 16:32:21 -0700 | [diff] [blame] | 225 | }; |
| 226 | struct mpi3_nvme_encapsulated_error_reply { |
| 227 | __le16 host_tag; |
| 228 | __u8 ioc_use_only02; |
| 229 | __u8 function; |
| 230 | __le16 ioc_use_only04; |
| 231 | __u8 ioc_use_only06; |
| 232 | __u8 msg_flags; |
| 233 | __le16 ioc_use_only08; |
| 234 | __le16 ioc_status; |
| 235 | __le32 ioc_log_info; |
| 236 | __le32 nvme_completion_entry[4]; |
| 237 | }; |
| 238 | #define MPI3MR_NVME_PRP_SIZE 8 |
| 239 | #define MPI3MR_NVME_CMD_PRP1_OFFSET 24 |
| 240 | #define MPI3MR_NVME_CMD_PRP2_OFFSET 32 |
| 241 | #define MPI3MR_NVME_CMD_SGL_OFFSET 24 |
| 242 | #define MPI3MR_NVME_DATA_FORMAT_PRP 0 |
| 243 | #define MPI3MR_NVME_DATA_FORMAT_SGL1 1 |
| 244 | #define MPI3MR_NVME_DATA_FORMAT_SGL2 2 |
Christopher Ferris | b830ddf | 2024-03-28 11:48:08 -0700 | [diff] [blame] | 245 | #define MPI3MR_NVMESGL_DATA_SEGMENT 0x00 |
| 246 | #define MPI3MR_NVMESGL_LAST_SEGMENT 0x03 |
Christopher Ferris | 80ae69d | 2022-08-02 16:32:21 -0700 | [diff] [blame] | 247 | struct mpi3_scsi_task_mgmt_request { |
| 248 | __le16 host_tag; |
| 249 | __u8 ioc_use_only02; |
| 250 | __u8 function; |
| 251 | __le16 ioc_use_only04; |
| 252 | __u8 ioc_use_only06; |
| 253 | __u8 msg_flags; |
| 254 | __le16 change_count; |
| 255 | __le16 dev_handle; |
| 256 | __le16 task_host_tag; |
| 257 | __u8 task_type; |
| 258 | __u8 reserved0f; |
| 259 | __le16 task_request_queue_id; |
| 260 | __le16 reserved12; |
| 261 | __le32 reserved14; |
| 262 | __u8 lun[8]; |
| 263 | }; |
| 264 | #define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08) |
| 265 | #define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) |
| 266 | #define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02) |
| 267 | #define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) |
| 268 | #define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) |
| 269 | #define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) |
| 270 | #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) |
| 271 | #define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08) |
| 272 | #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09) |
| 273 | #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a) |
| 274 | #define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b) |
| 275 | struct mpi3_scsi_task_mgmt_reply { |
| 276 | __le16 host_tag; |
| 277 | __u8 ioc_use_only02; |
| 278 | __u8 function; |
| 279 | __le16 ioc_use_only04; |
| 280 | __u8 ioc_use_only06; |
| 281 | __u8 msg_flags; |
| 282 | __le16 ioc_use_only08; |
| 283 | __le16 ioc_status; |
| 284 | __le32 ioc_log_info; |
| 285 | __le32 termination_count; |
| 286 | __le32 response_data; |
| 287 | __le32 reserved18; |
| 288 | }; |
| 289 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00) |
| 290 | #define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02) |
| 291 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04) |
| 292 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05) |
| 293 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08) |
| 294 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09) |
| 295 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a) |
| 296 | #define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80) |
| 297 | #define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81) |
| 298 | #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) |
| 299 | #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) |
| 300 | #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) |
| 301 | #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) |
| 302 | #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) |
| 303 | #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) |
| 304 | #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) |
| 305 | #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) |
| 306 | #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) |
| 307 | #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) |
| 308 | #define MPI3_PEL_CLASS_DEBUG (0x00) |
| 309 | #define MPI3_PEL_CLASS_PROGRESS (0x01) |
| 310 | #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) |
| 311 | #define MPI3_PEL_CLASS_WARNING (0x03) |
| 312 | #define MPI3_PEL_CLASS_CRITICAL (0x04) |
| 313 | #define MPI3_PEL_CLASS_FATAL (0x05) |
| 314 | #define MPI3_PEL_CLASS_FAULT (0x06) |
| 315 | #define MPI3_BSG_FUNCTION_MGMT_PASSTHROUGH (0x0a) |
| 316 | #define MPI3_BSG_FUNCTION_SCSI_IO (0x20) |
| 317 | #define MPI3_BSG_FUNCTION_SCSI_TASK_MGMT (0x21) |
| 318 | #define MPI3_BSG_FUNCTION_SMP_PASSTHROUGH (0x22) |
| 319 | #define MPI3_BSG_FUNCTION_NVME_ENCAPSULATED (0x24) |
| 320 | #endif |