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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __SOUND_HDSPM_H
20#define __SOUND_HDSPM_H
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -070021#ifdef __linux__
Christopher Ferris05d08e92016-02-04 13:16:38 -080022#include <linux/types.h>
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -070023#endif
Ben Cheng655a7c02013-10-16 16:09:24 -070024#define HDSPM_MAX_CHANNELS 64
Christopher Ferris05d08e92016-02-04 13:16:38 -080025enum hdspm_io_type {
Tao Baod7db5942015-01-28 10:07:51 -080026 MADI,
27 MADIface,
28 AIO,
Christopher Ferris05d08e92016-02-04 13:16:38 -080029 AES32,
Tao Baod7db5942015-01-28 10:07:51 -080030 RayDAT
Ben Cheng655a7c02013-10-16 16:09:24 -070031};
32enum hdspm_speed {
Christopher Ferris05d08e92016-02-04 13:16:38 -080033 ss,
Tao Baod7db5942015-01-28 10:07:51 -080034 ds,
35 qs
Ben Cheng655a7c02013-10-16 16:09:24 -070036};
37struct hdspm_peak_rms {
Christopher Ferris05d08e92016-02-04 13:16:38 -080038 __u32 input_peaks[64];
39 __u32 playback_peaks[64];
40 __u32 output_peaks[64];
Christopher Ferris05d08e92016-02-04 13:16:38 -080041 __u64 input_rms[64];
42 __u64 playback_rms[64];
43 __u64 output_rms[64];
44 __u8 speed;
Tao Baod7db5942015-01-28 10:07:51 -080045 int status2;
Ben Cheng655a7c02013-10-16 16:09:24 -070046};
Tao Baod7db5942015-01-28 10:07:51 -080047#define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS _IOR('H', 0x42, struct hdspm_peak_rms)
Ben Cheng655a7c02013-10-16 16:09:24 -070048struct hdspm_config {
Christopher Ferris05d08e92016-02-04 13:16:38 -080049 unsigned char pref_sync_ref;
Tao Baod7db5942015-01-28 10:07:51 -080050 unsigned char wordclock_sync_check;
51 unsigned char madi_sync_check;
52 unsigned int system_sample_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -080053 unsigned int autosync_sample_rate;
Tao Baod7db5942015-01-28 10:07:51 -080054 unsigned char system_clock_mode;
55 unsigned char clock_source;
56 unsigned char autosync_ref;
Christopher Ferris05d08e92016-02-04 13:16:38 -080057 unsigned char line_out;
Tao Baod7db5942015-01-28 10:07:51 -080058 unsigned int passthru;
59 unsigned int analog_out;
Ben Cheng655a7c02013-10-16 16:09:24 -070060};
Christopher Ferris05d08e92016-02-04 13:16:38 -080061#define SNDRV_HDSPM_IOCTL_GET_CONFIG _IOR('H', 0x41, struct hdspm_config)
Ben Cheng655a7c02013-10-16 16:09:24 -070062enum hdspm_ltc_format {
Tao Baod7db5942015-01-28 10:07:51 -080063 format_invalid,
64 fps_24,
Christopher Ferris05d08e92016-02-04 13:16:38 -080065 fps_25,
Tao Baod7db5942015-01-28 10:07:51 -080066 fps_2997,
67 fps_30
Ben Cheng655a7c02013-10-16 16:09:24 -070068};
Christopher Ferris05d08e92016-02-04 13:16:38 -080069enum hdspm_ltc_frame {
Tao Baod7db5942015-01-28 10:07:51 -080070 frame_invalid,
71 drop_frame,
72 full_frame
Christopher Ferris05d08e92016-02-04 13:16:38 -080073};
Ben Cheng655a7c02013-10-16 16:09:24 -070074enum hdspm_ltc_input_format {
Tao Baod7db5942015-01-28 10:07:51 -080075 ntsc,
76 pal,
Christopher Ferris05d08e92016-02-04 13:16:38 -080077 no_video
Ben Cheng655a7c02013-10-16 16:09:24 -070078};
79struct hdspm_ltc {
Tao Baod7db5942015-01-28 10:07:51 -080080 unsigned int ltc;
Christopher Ferris05d08e92016-02-04 13:16:38 -080081 enum hdspm_ltc_format format;
Tao Baod7db5942015-01-28 10:07:51 -080082 enum hdspm_ltc_frame frame;
83 enum hdspm_ltc_input_format input_format;
Ben Cheng655a7c02013-10-16 16:09:24 -070084};
Christopher Ferris05d08e92016-02-04 13:16:38 -080085#define SNDRV_HDSPM_IOCTL_GET_LTC _IOR('H', 0x46, struct hdspm_ltc)
Ben Cheng655a7c02013-10-16 16:09:24 -070086enum hdspm_sync {
Tao Baod7db5942015-01-28 10:07:51 -080087 hdspm_sync_no_lock = 0,
88 hdspm_sync_lock = 1,
Christopher Ferris05d08e92016-02-04 13:16:38 -080089 hdspm_sync_sync = 2
Ben Cheng655a7c02013-10-16 16:09:24 -070090};
91enum hdspm_madi_input {
Tao Baod7db5942015-01-28 10:07:51 -080092 hdspm_input_optical = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -080093 hdspm_input_coax = 1
Ben Cheng655a7c02013-10-16 16:09:24 -070094};
95enum hdspm_madi_channel_format {
Tao Baod7db5942015-01-28 10:07:51 -080096 hdspm_format_ch_64 = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -080097 hdspm_format_ch_56 = 1
Ben Cheng655a7c02013-10-16 16:09:24 -070098};
99enum hdspm_madi_frame_format {
Tao Baod7db5942015-01-28 10:07:51 -0800100 hdspm_frame_48 = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800101 hdspm_frame_96 = 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700102};
103enum hdspm_syncsource {
Tao Baod7db5942015-01-28 10:07:51 -0800104 syncsource_wc = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800105 syncsource_madi = 1,
Tao Baod7db5942015-01-28 10:07:51 -0800106 syncsource_tco = 2,
107 syncsource_sync = 3,
108 syncsource_none = 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700109};
Ben Cheng655a7c02013-10-16 16:09:24 -0700110struct hdspm_status {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800111 __u8 card_type;
Tao Baod7db5942015-01-28 10:07:51 -0800112 enum hdspm_syncsource autosync_source;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113 __u64 card_clock;
114 __u32 master_period;
Tao Baod7db5942015-01-28 10:07:51 -0800115 union {
116 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800117 __u8 sync_wc;
118 __u8 sync_madi;
119 __u8 sync_tco;
120 __u8 sync_in;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800121 __u8 madi_input;
122 __u8 channel_format;
123 __u8 frame_format;
Tao Baod7db5942015-01-28 10:07:51 -0800124 } madi;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800125 } card_specific;
Ben Cheng655a7c02013-10-16 16:09:24 -0700126};
Tao Baod7db5942015-01-28 10:07:51 -0800127#define SNDRV_HDSPM_IOCTL_GET_STATUS _IOR('H', 0x47, struct hdspm_status)
Ben Cheng655a7c02013-10-16 16:09:24 -0700128#define HDSPM_ADDON_TCO 1
Christopher Ferris05d08e92016-02-04 13:16:38 -0800129struct hdspm_version {
130 __u8 card_type;
Tao Baod7db5942015-01-28 10:07:51 -0800131 char cardname[20];
132 unsigned int serial;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800133 unsigned short firmware_rev;
Tao Baod7db5942015-01-28 10:07:51 -0800134 int addons;
Ben Cheng655a7c02013-10-16 16:09:24 -0700135};
136#define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x48, struct hdspm_version)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800137#define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS
Ben Cheng655a7c02013-10-16 16:09:24 -0700138struct hdspm_channelfader {
Tao Baod7db5942015-01-28 10:07:51 -0800139 unsigned int in[HDSPM_MIXER_CHANNELS];
140 unsigned int pb[HDSPM_MIXER_CHANNELS];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141};
Ben Cheng655a7c02013-10-16 16:09:24 -0700142struct hdspm_mixer {
Tao Baod7db5942015-01-28 10:07:51 -0800143 struct hdspm_channelfader ch[HDSPM_MIXER_CHANNELS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700144};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800145struct hdspm_mixer_ioctl {
Tao Baod7db5942015-01-28 10:07:51 -0800146 struct hdspm_mixer * mixer;
Ben Cheng655a7c02013-10-16 16:09:24 -0700147};
148#define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct hdspm_mixer_ioctl)
Ben Cheng655a7c02013-10-16 16:09:24 -0700149#endif