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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_LINUX_SERIAL_H
20#define _UAPI_LINUX_SERIAL_H
21#include <linux/types.h>
22#include <linux/tty_flags.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070023struct serial_struct {
Tao Baod7db5942015-01-28 10:07:51 -080024 int type;
25 int line;
26 unsigned int port;
Tao Baod7db5942015-01-28 10:07:51 -080027 int irq;
28 int flags;
29 int xmit_fifo_size;
30 int custom_divisor;
Tao Baod7db5942015-01-28 10:07:51 -080031 int baud_base;
32 unsigned short close_delay;
33 char io_type;
34 char reserved_char[1];
Tao Baod7db5942015-01-28 10:07:51 -080035 int hub6;
36 unsigned short closing_wait;
37 unsigned short closing_wait2;
38 unsigned char * iomem_base;
Tao Baod7db5942015-01-28 10:07:51 -080039 unsigned short iomem_reg_shift;
40 unsigned int port_high;
41 unsigned long iomap_base;
Ben Cheng655a7c02013-10-16 16:09:24 -070042};
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define ASYNC_CLOSING_WAIT_INF 0
44#define ASYNC_CLOSING_WAIT_NONE 65535
45#define PORT_UNKNOWN 0
46#define PORT_8250 1
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define PORT_16450 2
48#define PORT_16550 3
49#define PORT_16550A 4
50#define PORT_CIRRUS 5
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define PORT_16650 6
52#define PORT_16650V2 7
53#define PORT_16750 8
54#define PORT_STARTECH 9
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define PORT_16C950 10
56#define PORT_16654 11
57#define PORT_16850 12
58#define PORT_RSA 13
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define PORT_MAX 13
60#define SERIAL_IO_PORT 0
61#define SERIAL_IO_HUB6 1
62#define SERIAL_IO_MEM 2
Christopher Ferris05d08e92016-02-04 13:16:38 -080063#define SERIAL_IO_MEM32 3
64#define SERIAL_IO_AU 4
65#define SERIAL_IO_TSI 5
66#define SERIAL_IO_MEM32BE 6
Christopher Ferris106b3a82016-08-24 12:15:38 -070067#define SERIAL_IO_MEM16 7
Ben Cheng655a7c02013-10-16 16:09:24 -070068#define UART_CLEAR_FIFO 0x01
69#define UART_USE_FIFO 0x02
70#define UART_STARTECH 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -070071#define UART_NATSEMI 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -070072struct serial_multiport_struct {
Tao Baod7db5942015-01-28 10:07:51 -080073 int irq;
74 int port1;
Christopher Ferris106b3a82016-08-24 12:15:38 -070075 unsigned char mask1, match1;
Tao Baod7db5942015-01-28 10:07:51 -080076 int port2;
77 unsigned char mask2, match2;
78 int port3;
Christopher Ferris106b3a82016-08-24 12:15:38 -070079 unsigned char mask3, match3;
Tao Baod7db5942015-01-28 10:07:51 -080080 int port4;
81 unsigned char mask4, match4;
82 int port_monitor;
Christopher Ferris106b3a82016-08-24 12:15:38 -070083 int reserved[32];
Ben Cheng655a7c02013-10-16 16:09:24 -070084};
85struct serial_icounter_struct {
Tao Baod7db5942015-01-28 10:07:51 -080086 int cts, dsr, rng, dcd;
Christopher Ferris106b3a82016-08-24 12:15:38 -070087 int rx, tx;
Tao Baod7db5942015-01-28 10:07:51 -080088 int frame, overrun, parity, brk;
89 int buf_overrun;
90 int reserved[9];
Christopher Ferris106b3a82016-08-24 12:15:38 -070091};
Ben Cheng655a7c02013-10-16 16:09:24 -070092struct serial_rs485 {
Tao Baod7db5942015-01-28 10:07:51 -080093 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -070094#define SER_RS485_ENABLED (1 << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -070095#define SER_RS485_RTS_ON_SEND (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -070096#define SER_RS485_RTS_AFTER_SEND (1 << 2)
97#define SER_RS485_RX_DURING_TX (1 << 4)
Christopher Ferris1308ad32017-11-14 17:32:13 -080098#define SER_RS485_TERMINATE_BUS (1 << 5)
Tao Baod7db5942015-01-28 10:07:51 -080099 __u32 delay_rts_before_send;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700100 __u32 delay_rts_after_send;
Tao Baod7db5942015-01-28 10:07:51 -0800101 __u32 padding[5];
Ben Cheng655a7c02013-10-16 16:09:24 -0700102};
Christopher Ferris86a48372019-01-10 14:14:59 -0800103struct serial_iso7816 {
104 __u32 flags;
105#define SER_ISO7816_ENABLED (1 << 0)
106#define SER_ISO7816_T_PARAM (0x0f << 4)
107#define SER_ISO7816_T(t) (((t) & 0x0f) << 4)
108 __u32 tg;
109 __u32 sc_fi;
110 __u32 sc_di;
111 __u32 clk;
112 __u32 reserved[5];
113};
Ben Cheng655a7c02013-10-16 16:09:24 -0700114#endif