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Serban Constantinescu1c4f1012013-10-11 10:44:43 +01001/*-
2 * Copyright (c) 2004 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: libm/aarch64/fenv.c $
27 */
28
Christopher Ferrisfa775292015-10-23 15:42:27 -070029#include <stdint.h>
Serban Constantinescu1c4f1012013-10-11 10:44:43 +010030#include <fenv.h>
31
Serban Constantinescua147a1d2014-06-08 16:55:22 +010032#define FPCR_RMODE_SHIFT 22
33
34const fenv_t __fe_dfl_env = { 0 /* control */, 0 /* status */};
35
36typedef __uint32_t fpu_control_t; // FPCR, Floating-point Control Register.
37typedef __uint32_t fpu_status_t; // FPSR, Floating-point Status Register.
38
Christopher Ferrisfa775292015-10-23 15:42:27 -070039#define __get(REGISTER, __value) { \
40 uint64_t __value64; \
41 __asm__ __volatile__("mrs %0," REGISTER : "=r" (__value64)); \
42 __value = (__uint32_t) __value64; \
43}
44#define __get_fpcr(__fpcr) __get("fpcr", __fpcr)
45#define __get_fpsr(__fpsr) __get("fpsr", __fpsr)
46
47#define __set(REGISTER, __value) { \
48 uint64_t __value64 = __value; \
49 __asm__ __volatile__("msr " REGISTER ",%0" : : "ri" (__value64)); \
50}
51#define __set_fpcr(__fpcr) __set("fpcr", __fpcr)
52#define __set_fpsr(__fpsr) __set("fpsr", __fpsr)
Serban Constantinescua147a1d2014-06-08 16:55:22 +010053
54int fegetenv(fenv_t* envp) {
55 __get_fpcr(envp->__control);
56 __get_fpsr(envp->__status);
Calin Juravle2d367902014-02-25 14:49:41 +000057 return 0;
58}
59
Serban Constantinescua147a1d2014-06-08 16:55:22 +010060int fesetenv(const fenv_t* envp) {
61 fpu_control_t fpcr;
62
63 __get_fpcr(fpcr);
64 if (envp->__control != fpcr) {
65 __set_fpcr(envp->__control);
66 }
67 __set_fpsr(envp->__status);
Calin Juravle2d367902014-02-25 14:49:41 +000068 return 0;
69}
70
Serban Constantinescua147a1d2014-06-08 16:55:22 +010071int feclearexcept(int excepts) {
72 fpu_status_t fpsr;
73
74 excepts &= FE_ALL_EXCEPT;
75 __get_fpsr(fpsr);
76 fpsr &= ~excepts;
77 __set_fpsr(fpsr);
Calin Juravle2d367902014-02-25 14:49:41 +000078 return 0;
79}
80
Serban Constantinescua147a1d2014-06-08 16:55:22 +010081int fegetexceptflag(fexcept_t* flagp, int excepts) {
82 fpu_status_t fpsr;
83
84 excepts &= FE_ALL_EXCEPT;
85 __get_fpsr(fpsr);
86 *flagp = fpsr & excepts;
Calin Juravle2d367902014-02-25 14:49:41 +000087 return 0;
88}
89
Serban Constantinescua147a1d2014-06-08 16:55:22 +010090int fesetexceptflag(const fexcept_t* flagp, int excepts) {
91 fpu_status_t fpsr;
92
93 excepts &= FE_ALL_EXCEPT;
94 __get_fpsr(fpsr);
95 fpsr &= ~excepts;
96 fpsr |= *flagp & excepts;
97 __set_fpsr(fpsr);
Calin Juravle2d367902014-02-25 14:49:41 +000098 return 0;
99}
100
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100101int feraiseexcept(int excepts) {
102 fexcept_t ex = excepts;
103
104 fesetexceptflag(&ex, excepts);
Calin Juravle2d367902014-02-25 14:49:41 +0000105 return 0;
106}
107
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100108int fetestexcept(int excepts) {
109 fpu_status_t fpsr;
110
111 excepts &= FE_ALL_EXCEPT;
112 __get_fpsr(fpsr);
113 return (fpsr & excepts);
Calin Juravle2d367902014-02-25 14:49:41 +0000114}
115
116int fegetround(void) {
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100117 fpu_control_t fpcr;
118
119 __get_fpcr(fpcr);
120 return ((fpcr >> FPCR_RMODE_SHIFT) & FE_TOWARDZERO);
Calin Juravle2d367902014-02-25 14:49:41 +0000121}
122
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100123int fesetround(int round) {
124 fpu_control_t fpcr, new_fpcr;
125
126 round &= FE_TOWARDZERO;
127 __get_fpcr(fpcr);
128 new_fpcr = fpcr & ~(FE_TOWARDZERO << FPCR_RMODE_SHIFT);
129 new_fpcr |= (round << FPCR_RMODE_SHIFT);
130 if (new_fpcr != fpcr) {
131 __set_fpcr(new_fpcr);
132 }
Calin Juravle2d367902014-02-25 14:49:41 +0000133 return 0;
134}
135
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100136int feholdexcept(fenv_t* envp) {
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100137 fpu_status_t fpsr;
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100138 __get_fpsr(fpsr);
Elliott Hughesb6c7f6e2017-11-03 16:46:32 -0700139 fpu_control_t fpcr;
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100140 __get_fpcr(fpcr);
Elliott Hughesb6c7f6e2017-11-03 16:46:32 -0700141 fenv_t env = { .__status = fpsr, .__control = fpcr };
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100142 *envp = env;
143
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100144 // Clear all exceptions.
145 fpsr &= ~FE_ALL_EXCEPT;
146 __set_fpsr(fpsr);
Calin Juravle2d367902014-02-25 14:49:41 +0000147 return 0;
148}
149
Serban Constantinescua147a1d2014-06-08 16:55:22 +0100150int feupdateenv(const fenv_t* envp) {
151 fpu_status_t fpsr;
152 fpu_control_t fpcr;
153
154 // Set FPU Control register.
155 __get_fpcr(fpcr);
156 if (envp->__control != fpcr) {
157 __set_fpcr(envp->__control);
158 }
159
160 // Set FPU Status register to status | currently raised exceptions.
161 __get_fpsr(fpsr);
162 fpsr = envp->__status | (fpsr & FE_ALL_EXCEPT);
163 __set_fpsr(fpsr);
Calin Juravle2d367902014-02-25 14:49:41 +0000164 return 0;
165}
166
Elliott Hughesb6c7f6e2017-11-03 16:46:32 -0700167int feenableexcept(int mask __unused) {
168 return -1;
Calin Juravle2d367902014-02-25 14:49:41 +0000169}
170
Elliott Hughesb6c7f6e2017-11-03 16:46:32 -0700171int fedisableexcept(int mask __unused) {
172 return 0;
Calin Juravle2d367902014-02-25 14:49:41 +0000173}
174
175int fegetexcept(void) {
Elliott Hughesb6c7f6e2017-11-03 16:46:32 -0700176 return 0;
Calin Juravle2d367902014-02-25 14:49:41 +0000177}