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gerrit.omnirom.org / android_bionic / aeddbcfb2cbd118b5f97c0e586bcf19862ad5247 / . / libc / kernel / uapi / drm / lima_drm.h
blob: bb70cf79dd118db8cb138868dfe5e810bbe9d0e4 [file] [log] [blame]
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700[diff] [blame^]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __LIMA_DRM_H__
20#define __LIMA_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25enum drm_lima_param_gpu_id {
26 DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
27 DRM_LIMA_PARAM_GPU_ID_MALI400,
28 DRM_LIMA_PARAM_GPU_ID_MALI450,
29};
30enum drm_lima_param {
31 DRM_LIMA_PARAM_GPU_ID,
32 DRM_LIMA_PARAM_NUM_PP,
33 DRM_LIMA_PARAM_GP_VERSION,
34 DRM_LIMA_PARAM_PP_VERSION,
35};
36struct drm_lima_get_param {
37 __u32 param;
38 __u32 pad;
39 __u64 value;
40};
41struct drm_lima_gem_create {
42 __u32 size;
43 __u32 flags;
44 __u32 handle;
45 __u32 pad;
46};
47struct drm_lima_gem_info {
48 __u32 handle;
49 __u32 va;
50 __u64 offset;
51};
52#define LIMA_SUBMIT_BO_READ 0x01
53#define LIMA_SUBMIT_BO_WRITE 0x02
54struct drm_lima_gem_submit_bo {
55 __u32 handle;
56 __u32 flags;
57};
58#define LIMA_GP_FRAME_REG_NUM 6
59struct drm_lima_gp_frame {
60 __u32 frame[LIMA_GP_FRAME_REG_NUM];
61};
62#define LIMA_PP_FRAME_REG_NUM 23
63#define LIMA_PP_WB_REG_NUM 12
64struct drm_lima_m400_pp_frame {
65 __u32 frame[LIMA_PP_FRAME_REG_NUM];
66 __u32 num_pp;
67 __u32 wb[3 * LIMA_PP_WB_REG_NUM];
68 __u32 plbu_array_address[4];
69 __u32 fragment_stack_address[4];
70};
71struct drm_lima_m450_pp_frame {
72 __u32 frame[LIMA_PP_FRAME_REG_NUM];
73 __u32 num_pp;
74 __u32 wb[3 * LIMA_PP_WB_REG_NUM];
75 __u32 use_dlbu;
76 __u32 _pad;
77 union {
78 __u32 plbu_array_address[8];
79 __u32 dlbu_regs[4];
80 };
81 __u32 fragment_stack_address[8];
82};
83#define LIMA_PIPE_GP 0x00
84#define LIMA_PIPE_PP 0x01
85#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
86struct drm_lima_gem_submit {
87 __u32 ctx;
88 __u32 pipe;
89 __u32 nr_bos;
90 __u32 frame_size;
91 __u64 bos;
92 __u64 frame;
93 __u32 flags;
94 __u32 out_sync;
95 __u32 in_sync[2];
96};
97#define LIMA_GEM_WAIT_READ 0x01
98#define LIMA_GEM_WAIT_WRITE 0x02
99struct drm_lima_gem_wait {
100 __u32 handle;
101 __u32 op;
102 __s64 timeout_ns;
103};
104struct drm_lima_ctx_create {
105 __u32 id;
106 __u32 _pad;
107};
108struct drm_lima_ctx_free {
109 __u32 id;
110 __u32 _pad;
111};
112#define DRM_LIMA_GET_PARAM 0x00
113#define DRM_LIMA_GEM_CREATE 0x01
114#define DRM_LIMA_GEM_INFO 0x02
115#define DRM_LIMA_GEM_SUBMIT 0x03
116#define DRM_LIMA_GEM_WAIT 0x04
117#define DRM_LIMA_CTX_CREATE 0x05
118#define DRM_LIMA_CTX_FREE 0x06
119#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
120#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
121#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
122#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
123#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
124#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
125#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
126#ifdef __cplusplus
127}
128#endif
129#endif