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Christopher Ferrisa9750ed2021-05-03 14:02:49 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_ACRN_H
20#define _UAPI_ACRN_H
21#include <linux/types.h>
22#include <linux/uuid.h>
23#define ACRN_IO_REQUEST_MAX 16
24#define ACRN_IOREQ_STATE_PENDING 0
25#define ACRN_IOREQ_STATE_COMPLETE 1
26#define ACRN_IOREQ_STATE_PROCESSING 2
27#define ACRN_IOREQ_STATE_FREE 3
28#define ACRN_IOREQ_TYPE_PORTIO 0
29#define ACRN_IOREQ_TYPE_MMIO 1
30#define ACRN_IOREQ_TYPE_PCICFG 2
31#define ACRN_IOREQ_DIR_READ 0
32#define ACRN_IOREQ_DIR_WRITE 1
33struct acrn_mmio_request {
34 __u32 direction;
35 __u32 reserved;
36 __u64 address;
37 __u64 size;
38 __u64 value;
39};
40struct acrn_pio_request {
41 __u32 direction;
42 __u32 reserved;
43 __u64 address;
44 __u64 size;
45 __u32 value;
46};
47struct acrn_pci_request {
48 __u32 direction;
49 __u32 reserved[3];
50 __u64 size;
51 __u32 value;
52 __u32 bus;
53 __u32 dev;
54 __u32 func;
55 __u32 reg;
56};
57struct acrn_io_request {
58 __u32 type;
59 __u32 completion_polling;
60 __u32 reserved0[14];
61 union {
62 struct acrn_pio_request pio_request;
63 struct acrn_pci_request pci_request;
64 struct acrn_mmio_request mmio_request;
65 __u64 data[8];
66 } reqs;
67 __u32 reserved1;
68 __u32 kernel_handled;
69 __u32 processed;
70} __attribute__((aligned(256)));
71struct acrn_io_request_buffer {
72 union {
73 struct acrn_io_request req_slot[ACRN_IO_REQUEST_MAX];
74 __u8 reserved[4096];
75 };
76};
77struct acrn_ioreq_notify {
78 __u16 vmid;
79 __u16 reserved;
80 __u32 vcpu;
81};
82struct acrn_vm_creation {
83 __u16 vmid;
84 __u16 reserved0;
85 __u16 vcpu_num;
86 __u16 reserved1;
87 guid_t uuid;
88 __u64 vm_flag;
89 __u64 ioreq_buf;
90 __u64 cpu_affinity;
91};
92struct acrn_gp_regs {
93 __le64 rax;
94 __le64 rcx;
95 __le64 rdx;
96 __le64 rbx;
97 __le64 rsp;
98 __le64 rbp;
99 __le64 rsi;
100 __le64 rdi;
101 __le64 r8;
102 __le64 r9;
103 __le64 r10;
104 __le64 r11;
105 __le64 r12;
106 __le64 r13;
107 __le64 r14;
108 __le64 r15;
109};
110struct acrn_descriptor_ptr {
111 __le16 limit;
112 __le64 base;
113 __le16 reserved[3];
114} __attribute__((__packed__));
115struct acrn_regs {
116 struct acrn_gp_regs gprs;
117 struct acrn_descriptor_ptr gdt;
118 struct acrn_descriptor_ptr idt;
119 __le64 rip;
120 __le64 cs_base;
121 __le64 cr0;
122 __le64 cr4;
123 __le64 cr3;
124 __le64 ia32_efer;
125 __le64 rflags;
126 __le64 reserved_64[4];
127 __le32 cs_ar;
128 __le32 cs_limit;
129 __le32 reserved_32[3];
130 __le16 cs_sel;
131 __le16 ss_sel;
132 __le16 ds_sel;
133 __le16 es_sel;
134 __le16 fs_sel;
135 __le16 gs_sel;
136 __le16 ldt_sel;
137 __le16 tr_sel;
138};
139struct acrn_vcpu_regs {
140 __u16 vcpu_id;
141 __u16 reserved[3];
142 struct acrn_regs vcpu_regs;
143};
144#define ACRN_MEM_ACCESS_RIGHT_MASK 0x00000007U
145#define ACRN_MEM_ACCESS_READ 0x00000001U
146#define ACRN_MEM_ACCESS_WRITE 0x00000002U
147#define ACRN_MEM_ACCESS_EXEC 0x00000004U
148#define ACRN_MEM_ACCESS_RWX (ACRN_MEM_ACCESS_READ | ACRN_MEM_ACCESS_WRITE | ACRN_MEM_ACCESS_EXEC)
149#define ACRN_MEM_TYPE_MASK 0x000007C0U
150#define ACRN_MEM_TYPE_WB 0x00000040U
151#define ACRN_MEM_TYPE_WT 0x00000080U
152#define ACRN_MEM_TYPE_UC 0x00000100U
153#define ACRN_MEM_TYPE_WC 0x00000200U
154#define ACRN_MEM_TYPE_WP 0x00000400U
155#define ACRN_MEMMAP_RAM 0
156#define ACRN_MEMMAP_MMIO 1
157struct acrn_vm_memmap {
158 __u32 type;
159 __u32 attr;
160 __u64 user_vm_pa;
161 union {
162 __u64 service_vm_pa;
163 __u64 vma_base;
164 };
165 __u64 len;
166};
167#define ACRN_PTDEV_IRQ_INTX 0
168#define ACRN_PTDEV_IRQ_MSI 1
169#define ACRN_PTDEV_IRQ_MSIX 2
170struct acrn_ptdev_irq {
171 __u32 type;
172 __u16 virt_bdf;
173 __u16 phys_bdf;
174 struct {
175 __u32 virt_pin;
176 __u32 phys_pin;
177 __u32 is_pic_pin;
178 } intx;
179};
180#define ACRN_PTDEV_QUIRK_ASSIGN (1U << 0)
Christopher Ferrisa4792612022-01-10 13:51:15 -0800181#define ACRN_MMIODEV_RES_NUM 3
Christopher Ferrisa9750ed2021-05-03 14:02:49 -0700182#define ACRN_PCI_NUM_BARS 6
183struct acrn_pcidev {
184 __u32 type;
185 __u16 virt_bdf;
186 __u16 phys_bdf;
187 __u8 intr_line;
188 __u8 intr_pin;
189 __u32 bar[ACRN_PCI_NUM_BARS];
190};
Christopher Ferrisa4792612022-01-10 13:51:15 -0800191struct acrn_mmiodev {
192 __u8 name[8];
193 struct {
194 __u64 user_vm_pa;
195 __u64 service_vm_pa;
196 __u64 size;
197 __u64 mem_type;
198 } res[ACRN_MMIODEV_RES_NUM];
199};
200struct acrn_vdev {
201 union {
202 __u64 value;
203 struct {
204 __le16 vendor;
205 __le16 device;
206 __le32 legacy_id;
207 } fields;
208 } id;
209 __u64 slot;
210 __u32 io_addr[ACRN_PCI_NUM_BARS];
211 __u32 io_size[ACRN_PCI_NUM_BARS];
212 __u8 args[128];
213};
Christopher Ferrisa9750ed2021-05-03 14:02:49 -0700214struct acrn_msi_entry {
215 __u64 msi_addr;
216 __u64 msi_data;
217};
218struct acrn_acpi_generic_address {
219 __u8 space_id;
220 __u8 bit_width;
221 __u8 bit_offset;
222 __u8 access_size;
223 __u64 address;
224} __attribute__((__packed__));
225struct acrn_cstate_data {
226 struct acrn_acpi_generic_address cx_reg;
227 __u8 type;
228 __u32 latency;
229 __u64 power;
230};
231struct acrn_pstate_data {
232 __u64 core_frequency;
233 __u64 power;
234 __u64 transition_latency;
235 __u64 bus_master_latency;
236 __u64 control;
237 __u64 status;
238};
239#define PMCMD_TYPE_MASK 0x000000ff
240enum acrn_pm_cmd_type {
241 ACRN_PMCMD_GET_PX_CNT,
242 ACRN_PMCMD_GET_PX_DATA,
243 ACRN_PMCMD_GET_CX_CNT,
244 ACRN_PMCMD_GET_CX_DATA,
245};
246#define ACRN_IOEVENTFD_FLAG_PIO 0x01
247#define ACRN_IOEVENTFD_FLAG_DATAMATCH 0x02
248#define ACRN_IOEVENTFD_FLAG_DEASSIGN 0x04
249struct acrn_ioeventfd {
250 __u32 fd;
251 __u32 flags;
252 __u64 addr;
253 __u32 len;
254 __u32 reserved;
255 __u64 data;
256};
257#define ACRN_IRQFD_FLAG_DEASSIGN 0x01
258struct acrn_irqfd {
259 __s32 fd;
260 __u32 flags;
261 struct acrn_msi_entry msi;
262};
263#define ACRN_IOCTL_TYPE 0xA2
264#define ACRN_IOCTL_CREATE_VM _IOWR(ACRN_IOCTL_TYPE, 0x10, struct acrn_vm_creation)
265#define ACRN_IOCTL_DESTROY_VM _IO(ACRN_IOCTL_TYPE, 0x11)
266#define ACRN_IOCTL_START_VM _IO(ACRN_IOCTL_TYPE, 0x12)
267#define ACRN_IOCTL_PAUSE_VM _IO(ACRN_IOCTL_TYPE, 0x13)
268#define ACRN_IOCTL_RESET_VM _IO(ACRN_IOCTL_TYPE, 0x15)
269#define ACRN_IOCTL_SET_VCPU_REGS _IOW(ACRN_IOCTL_TYPE, 0x16, struct acrn_vcpu_regs)
270#define ACRN_IOCTL_INJECT_MSI _IOW(ACRN_IOCTL_TYPE, 0x23, struct acrn_msi_entry)
271#define ACRN_IOCTL_VM_INTR_MONITOR _IOW(ACRN_IOCTL_TYPE, 0x24, unsigned long)
272#define ACRN_IOCTL_SET_IRQLINE _IOW(ACRN_IOCTL_TYPE, 0x25, __u64)
273#define ACRN_IOCTL_NOTIFY_REQUEST_FINISH _IOW(ACRN_IOCTL_TYPE, 0x31, struct acrn_ioreq_notify)
274#define ACRN_IOCTL_CREATE_IOREQ_CLIENT _IO(ACRN_IOCTL_TYPE, 0x32)
275#define ACRN_IOCTL_ATTACH_IOREQ_CLIENT _IO(ACRN_IOCTL_TYPE, 0x33)
276#define ACRN_IOCTL_DESTROY_IOREQ_CLIENT _IO(ACRN_IOCTL_TYPE, 0x34)
277#define ACRN_IOCTL_CLEAR_VM_IOREQ _IO(ACRN_IOCTL_TYPE, 0x35)
278#define ACRN_IOCTL_SET_MEMSEG _IOW(ACRN_IOCTL_TYPE, 0x41, struct acrn_vm_memmap)
279#define ACRN_IOCTL_UNSET_MEMSEG _IOW(ACRN_IOCTL_TYPE, 0x42, struct acrn_vm_memmap)
280#define ACRN_IOCTL_SET_PTDEV_INTR _IOW(ACRN_IOCTL_TYPE, 0x53, struct acrn_ptdev_irq)
281#define ACRN_IOCTL_RESET_PTDEV_INTR _IOW(ACRN_IOCTL_TYPE, 0x54, struct acrn_ptdev_irq)
282#define ACRN_IOCTL_ASSIGN_PCIDEV _IOW(ACRN_IOCTL_TYPE, 0x55, struct acrn_pcidev)
283#define ACRN_IOCTL_DEASSIGN_PCIDEV _IOW(ACRN_IOCTL_TYPE, 0x56, struct acrn_pcidev)
Christopher Ferrisa4792612022-01-10 13:51:15 -0800284#define ACRN_IOCTL_ASSIGN_MMIODEV _IOW(ACRN_IOCTL_TYPE, 0x57, struct acrn_mmiodev)
285#define ACRN_IOCTL_DEASSIGN_MMIODEV _IOW(ACRN_IOCTL_TYPE, 0x58, struct acrn_mmiodev)
286#define ACRN_IOCTL_CREATE_VDEV _IOW(ACRN_IOCTL_TYPE, 0x59, struct acrn_vdev)
287#define ACRN_IOCTL_DESTROY_VDEV _IOW(ACRN_IOCTL_TYPE, 0x5A, struct acrn_vdev)
Christopher Ferrisa9750ed2021-05-03 14:02:49 -0700288#define ACRN_IOCTL_PM_GET_CPU_STATE _IOWR(ACRN_IOCTL_TYPE, 0x60, __u64)
289#define ACRN_IOCTL_IOEVENTFD _IOW(ACRN_IOCTL_TYPE, 0x70, struct acrn_ioeventfd)
290#define ACRN_IOCTL_IRQFD _IOW(ACRN_IOCTL_TYPE, 0x71, struct acrn_irqfd)
291#endif