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gerrit.omnirom.org / android_bionic / a3255e2cd6afc09b361a23ce1cd0b105eb8b89fc / . / libc / kernel / uapi / rdma / qedr-abi.h
blob: b9a84bba8e911227d76ff814fccd209bc7425447 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]7#ifndef __QEDR_USER_H__
8#define __QEDR_USER_H__
9#include <linux/types.h>
10#define QEDR_ABI_VERSION (8)
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800[diff] [blame]11enum qedr_alloc_ucontext_flags {
Christopher Ferris25c18d42020-10-14 17:42:58 -0700[diff] [blame]12 QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0,
13 QEDR_ALLOC_UCTX_DB_REC = 1 << 1,
14 QEDR_SUPPORT_DPM_SIZES = 1 << 2,
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800[diff] [blame]15};
16struct qedr_alloc_ucontext_req {
17 __u32 context_flags;
18 __u32 reserved;
19};
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700[diff] [blame]20#define QEDR_LDPM_MAX_SIZE (8192)
21#define QEDR_EDPM_TRANS_SIZE (64)
Christopher Ferris25c18d42020-10-14 17:42:58 -0700[diff] [blame]22#define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_INLINE_DATA_SIZE)
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700[diff] [blame]23enum qedr_rdma_dpm_type {
24 QEDR_DPM_TYPE_NONE = 0,
25 QEDR_DPM_TYPE_ROCE_ENHANCED = 1 << 0,
26 QEDR_DPM_TYPE_ROCE_LEGACY = 1 << 1,
27 QEDR_DPM_TYPE_IWARP_LEGACY = 1 << 2,
Christopher Ferris25c18d42020-10-14 17:42:58 -0700[diff] [blame]28 QEDR_DPM_TYPE_ROCE_EDPM_MODE = 1 << 3,
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700[diff] [blame]29 QEDR_DPM_SIZES_SET = 1 << 4,
30};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]31struct qedr_alloc_ucontext_resp {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]32 __aligned_u64 db_pa;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]33 __u32 db_size;
34 __u32 max_send_wr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]35 __u32 max_recv_wr;
36 __u32 max_srq_wr;
37 __u32 sges_per_send_wr;
38 __u32 sges_per_recv_wr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]39 __u32 sges_per_srq_wr;
40 __u32 max_cqes;
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700[diff] [blame]41 __u8 dpm_flags;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800[diff] [blame]42 __u8 wids_enabled;
43 __u16 wid_count;
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700[diff] [blame]44 __u16 ldpm_limit_size;
45 __u8 edpm_trans_size;
46 __u8 reserved;
Christopher Ferris25c18d42020-10-14 17:42:58 -0700[diff] [blame]47 __u16 edpm_limit_size;
48 __u8 padding[6];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]49};
50struct qedr_alloc_pd_ureq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]51 __aligned_u64 rsvd1;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]52};
53struct qedr_alloc_pd_uresp {
54 __u32 pd_id;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]55 __u32 reserved;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]56};
57struct qedr_create_cq_ureq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]58 __aligned_u64 addr;
59 __aligned_u64 len;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]60};
61struct qedr_create_cq_uresp {
62 __u32 db_offset;
63 __u16 icid;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]64 __u16 reserved;
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800[diff] [blame]65 __aligned_u64 db_rec_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]66};
67struct qedr_create_qp_ureq {
68 __u32 qp_handle_hi;
69 __u32 qp_handle_lo;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]70 __aligned_u64 sq_addr;
71 __aligned_u64 sq_len;
72 __aligned_u64 rq_addr;
73 __aligned_u64 rq_len;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]74};
75struct qedr_create_qp_uresp {
76 __u32 qp_id;
77 __u32 atomic_supported;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]78 __u32 sq_db_offset;
79 __u16 sq_icid;
80 __u32 rq_db_offset;
81 __u16 rq_icid;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]82 __u32 rq_db2_offset;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]83 __u32 reserved;
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800[diff] [blame]84 __aligned_u64 sq_db_rec_addr;
85 __aligned_u64 rq_db_rec_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]86};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]87struct qedr_create_srq_ureq {
88 __aligned_u64 prod_pair_addr;
89 __aligned_u64 srq_addr;
90 __aligned_u64 srq_len;
91};
92struct qedr_create_srq_uresp {
93 __u16 srq_id;
94 __u16 reserved0;
95 __u32 reserved1;
96};
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800[diff] [blame]97struct qedr_user_db_rec {
98 __aligned_u64 db_data;
99};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]100#endif