Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __VMWGFX_DRM_H__ |
| 20 | #define __VMWGFX_DRM_H__ |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 21 | #include "drm.h" |
| 22 | #ifdef __cplusplus |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 23 | #endif |
| 24 | #define DRM_VMW_MAX_SURFACE_FACES 6 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 25 | #define DRM_VMW_MAX_MIP_LEVELS 24 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 26 | #define DRM_VMW_GET_PARAM 0 |
| 27 | #define DRM_VMW_ALLOC_DMABUF 1 |
| 28 | #define DRM_VMW_UNREF_DMABUF 2 |
Christopher Ferris | 525ce91 | 2017-07-26 13:12:53 -0700 | [diff] [blame] | 29 | #define DRM_VMW_HANDLE_CLOSE 2 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 30 | #define DRM_VMW_CURSOR_BYPASS 3 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 31 | #define DRM_VMW_CONTROL_STREAM 4 |
| 32 | #define DRM_VMW_CLAIM_STREAM 5 |
| 33 | #define DRM_VMW_UNREF_STREAM 6 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 34 | #define DRM_VMW_CREATE_CONTEXT 7 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 35 | #define DRM_VMW_UNREF_CONTEXT 8 |
| 36 | #define DRM_VMW_CREATE_SURFACE 9 |
| 37 | #define DRM_VMW_UNREF_SURFACE 10 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 38 | #define DRM_VMW_REF_SURFACE 11 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 39 | #define DRM_VMW_EXECBUF 12 |
| 40 | #define DRM_VMW_GET_3D_CAP 13 |
| 41 | #define DRM_VMW_FENCE_WAIT 14 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 42 | #define DRM_VMW_FENCE_SIGNALED 15 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 43 | #define DRM_VMW_FENCE_UNREF 16 |
| 44 | #define DRM_VMW_FENCE_EVENT 17 |
| 45 | #define DRM_VMW_PRESENT 18 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 46 | #define DRM_VMW_PRESENT_READBACK 19 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 47 | #define DRM_VMW_UPDATE_LAYOUT 20 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 48 | #define DRM_VMW_CREATE_SHADER 21 |
| 49 | #define DRM_VMW_UNREF_SHADER 22 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 50 | #define DRM_VMW_GB_SURFACE_CREATE 23 |
| 51 | #define DRM_VMW_GB_SURFACE_REF 24 |
| 52 | #define DRM_VMW_SYNCCPU 25 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 53 | #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 54 | #define DRM_VMW_PARAM_NUM_STREAMS 0 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 55 | #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 |
| 56 | #define DRM_VMW_PARAM_3D 2 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 57 | #define DRM_VMW_PARAM_HW_CAPS 3 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 58 | #define DRM_VMW_PARAM_FIFO_CAPS 4 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 59 | #define DRM_VMW_PARAM_MAX_FB_SIZE 5 |
| 60 | #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 61 | #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 62 | #define DRM_VMW_PARAM_3D_CAPS_SIZE 8 |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 63 | #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 |
| 64 | #define DRM_VMW_PARAM_MAX_MOB_SIZE 10 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 65 | #define DRM_VMW_PARAM_SCREEN_TARGET 11 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 66 | #define DRM_VMW_PARAM_DX 12 |
Christopher Ferris | ba8d4f4 | 2014-09-03 19:56:49 -0700 | [diff] [blame] | 67 | enum drm_vmw_handle_type { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 68 | DRM_VMW_HANDLE_LEGACY = 0, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 69 | DRM_VMW_HANDLE_PRIME = 1 |
Christopher Ferris | ba8d4f4 | 2014-09-03 19:56:49 -0700 | [diff] [blame] | 70 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 71 | struct drm_vmw_getparam_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 72 | __u64 value; |
| 73 | __u32 param; |
| 74 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 75 | }; |
| 76 | struct drm_vmw_context_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 77 | __s32 cid; |
| 78 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 79 | }; |
| 80 | struct drm_vmw_surface_create_req { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 81 | __u32 flags; |
| 82 | __u32 format; |
| 83 | __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES]; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 84 | __u64 size_addr; |
| 85 | __s32 shareable; |
| 86 | __s32 scanout; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 87 | }; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 88 | struct drm_vmw_surface_arg { |
| 89 | __s32 sid; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 90 | enum drm_vmw_handle_type handle_type; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 91 | }; |
| 92 | struct drm_vmw_size { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 93 | __u32 width; |
| 94 | __u32 height; |
| 95 | __u32 depth; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 96 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 97 | }; |
| 98 | union drm_vmw_surface_create_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 99 | struct drm_vmw_surface_arg rep; |
| 100 | struct drm_vmw_surface_create_req req; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 101 | }; |
| 102 | union drm_vmw_surface_reference_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 103 | struct drm_vmw_surface_create_req rep; |
| 104 | struct drm_vmw_surface_arg req; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 105 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 106 | #define DRM_VMW_EXECBUF_VERSION 2 |
Christopher Ferris | 1308ad3 | 2017-11-14 17:32:13 -0800 | [diff] [blame] | 107 | #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0) |
| 108 | #define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 109 | struct drm_vmw_execbuf_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 110 | __u64 commands; |
| 111 | __u32 command_size; |
| 112 | __u32 throttle_us; |
| 113 | __u64 fence_rep; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 114 | __u32 version; |
| 115 | __u32 flags; |
| 116 | __u32 context_handle; |
Christopher Ferris | 1308ad3 | 2017-11-14 17:32:13 -0800 | [diff] [blame] | 117 | __s32 imported_fence_fd; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 118 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 119 | struct drm_vmw_fence_rep { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 120 | __u32 handle; |
| 121 | __u32 mask; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 122 | __u32 seqno; |
| 123 | __u32 passed_seqno; |
Christopher Ferris | 1308ad3 | 2017-11-14 17:32:13 -0800 | [diff] [blame] | 124 | __s32 fd; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 125 | __s32 error; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 126 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 127 | struct drm_vmw_alloc_dmabuf_req { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 128 | __u32 size; |
| 129 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 130 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 131 | struct drm_vmw_dmabuf_rep { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 132 | __u64 map_handle; |
| 133 | __u32 handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 134 | __u32 cur_gmr_id; |
| 135 | __u32 cur_gmr_offset; |
| 136 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 137 | }; |
| 138 | union drm_vmw_alloc_dmabuf_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 139 | struct drm_vmw_alloc_dmabuf_req req; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 140 | struct drm_vmw_dmabuf_rep rep; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 141 | }; |
| 142 | struct drm_vmw_unref_dmabuf_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 143 | __u32 handle; |
| 144 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 145 | }; |
| 146 | struct drm_vmw_rect { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 147 | __s32 x; |
| 148 | __s32 y; |
| 149 | __u32 w; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 150 | __u32 h; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 151 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 152 | struct drm_vmw_control_stream_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 153 | __u32 stream_id; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 154 | __u32 enabled; |
| 155 | __u32 flags; |
| 156 | __u32 color_key; |
| 157 | __u32 handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 158 | __u32 offset; |
| 159 | __s32 format; |
| 160 | __u32 size; |
| 161 | __u32 width; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 162 | __u32 height; |
| 163 | __u32 pitch[3]; |
| 164 | __u32 pad64; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 165 | struct drm_vmw_rect src; |
| 166 | struct drm_vmw_rect dst; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 167 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 168 | #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 169 | #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) |
| 170 | struct drm_vmw_cursor_bypass_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 171 | __u32 flags; |
| 172 | __u32 crtc_id; |
| 173 | __s32 xpos; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 174 | __s32 ypos; |
| 175 | __s32 xhot; |
| 176 | __s32 yhot; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 177 | }; |
| 178 | struct drm_vmw_stream_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 179 | __u32 stream_id; |
| 180 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 181 | }; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 182 | struct drm_vmw_get_3d_cap_arg { |
| 183 | __u64 buffer; |
| 184 | __u32 max_size; |
| 185 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 186 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 187 | #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 188 | #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 189 | #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) |
| 190 | struct drm_vmw_fence_wait_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 191 | __u32 handle; |
| 192 | __s32 cookie_valid; |
| 193 | __u64 kernel_cookie; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 194 | __u64 timeout_us; |
| 195 | __s32 lazy; |
| 196 | __s32 flags; |
| 197 | __s32 wait_options; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 198 | __s32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 199 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 200 | struct drm_vmw_fence_signaled_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 201 | __u32 handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 202 | __u32 flags; |
| 203 | __s32 signaled; |
| 204 | __u32 passed_seqno; |
| 205 | __u32 signaled_flags; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 206 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 207 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 208 | struct drm_vmw_fence_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 209 | __u32 handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 210 | __u32 pad64; |
| 211 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 212 | #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 213 | struct drm_vmw_event_fence { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 214 | struct drm_event base; |
| 215 | __u64 user_data; |
| 216 | __u32 tv_sec; |
| 217 | __u32 tv_usec; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 218 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 219 | #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 220 | struct drm_vmw_fence_event_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 221 | __u64 fence_rep; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 222 | __u64 user_data; |
| 223 | __u32 handle; |
| 224 | __u32 flags; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 225 | }; |
| 226 | struct drm_vmw_present_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 227 | __u32 fb_id; |
| 228 | __u32 sid; |
| 229 | __s32 dest_x; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 230 | __s32 dest_y; |
| 231 | __u64 clips_ptr; |
| 232 | __u32 num_clips; |
| 233 | __u32 pad64; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 234 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 235 | struct drm_vmw_present_readback_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 236 | __u32 fb_id; |
| 237 | __u32 num_clips; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 238 | __u64 clips_ptr; |
| 239 | __u64 fence_rep; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 240 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 241 | struct drm_vmw_update_layout_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 242 | __u32 num_outputs; |
| 243 | __u32 pad64; |
| 244 | __u64 rects; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 245 | }; |
| 246 | enum drm_vmw_shader_type { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 247 | drm_vmw_shader_type_vs = 0, |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 248 | drm_vmw_shader_type_ps, |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 249 | }; |
| 250 | struct drm_vmw_shader_create_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 251 | enum drm_vmw_shader_type shader_type; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 252 | __u32 size; |
| 253 | __u32 buffer_handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 254 | __u32 shader_handle; |
| 255 | __u64 offset; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 256 | }; |
| 257 | struct drm_vmw_shader_arg { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 258 | __u32 handle; |
| 259 | __u32 pad64; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 260 | }; |
| 261 | enum drm_vmw_surface_flags { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 262 | drm_vmw_surface_flag_shareable = (1 << 0), |
| 263 | drm_vmw_surface_flag_scanout = (1 << 1), |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 264 | drm_vmw_surface_flag_create_buffer = (1 << 2) |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 265 | }; |
| 266 | struct drm_vmw_gb_surface_create_req { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 267 | __u32 svga3d_flags; |
| 268 | __u32 format; |
| 269 | __u32 mip_levels; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 270 | enum drm_vmw_surface_flags drm_surface_flags; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 271 | __u32 multisample_count; |
| 272 | __u32 autogen_filter; |
| 273 | __u32 buffer_handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 274 | __u32 array_size; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 275 | struct drm_vmw_size base_size; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 276 | }; |
| 277 | struct drm_vmw_gb_surface_create_rep { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 278 | __u32 handle; |
| 279 | __u32 backup_size; |
| 280 | __u32 buffer_handle; |
| 281 | __u32 buffer_size; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 282 | __u64 buffer_map_handle; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 283 | }; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 284 | union drm_vmw_gb_surface_create_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 285 | struct drm_vmw_gb_surface_create_rep rep; |
| 286 | struct drm_vmw_gb_surface_create_req req; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 287 | }; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 288 | struct drm_vmw_gb_surface_ref_rep { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 289 | struct drm_vmw_gb_surface_create_req creq; |
| 290 | struct drm_vmw_gb_surface_create_rep crep; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 291 | }; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 292 | union drm_vmw_gb_surface_reference_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 293 | struct drm_vmw_gb_surface_ref_rep rep; |
| 294 | struct drm_vmw_surface_arg req; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 295 | }; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 296 | enum drm_vmw_synccpu_flags { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 297 | drm_vmw_synccpu_read = (1 << 0), |
| 298 | drm_vmw_synccpu_write = (1 << 1), |
| 299 | drm_vmw_synccpu_dontblock = (1 << 2), |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 300 | drm_vmw_synccpu_allow_cs = (1 << 3) |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 301 | }; |
| 302 | enum drm_vmw_synccpu_op { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 303 | drm_vmw_synccpu_grab, |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 304 | drm_vmw_synccpu_release |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 305 | }; |
| 306 | struct drm_vmw_synccpu_arg { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 307 | enum drm_vmw_synccpu_op op; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 308 | enum drm_vmw_synccpu_flags flags; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 309 | __u32 handle; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 310 | __u32 pad64; |
| 311 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 312 | enum drm_vmw_extended_context { |
| 313 | drm_vmw_context_legacy, |
| 314 | drm_vmw_context_dx |
| 315 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 316 | union drm_vmw_extended_context_arg { |
| 317 | enum drm_vmw_extended_context req; |
| 318 | struct drm_vmw_context_arg rep; |
| 319 | }; |
Christopher Ferris | 525ce91 | 2017-07-26 13:12:53 -0700 | [diff] [blame] | 320 | struct drm_vmw_handle_close_arg { |
| 321 | __u32 handle; |
| 322 | __u32 pad64; |
| 323 | }; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 324 | #ifdef __cplusplus |
| 325 | #endif |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 326 | #endif |