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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMWGFX_DRM_H__
20#define __VMWGFX_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
24#define DRM_VMW_MAX_SURFACE_FACES 6
Christopher Ferris38062f92014-07-09 15:33:25 -070025#define DRM_VMW_MAX_MIP_LEVELS 24
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define DRM_VMW_GET_PARAM 0
27#define DRM_VMW_ALLOC_DMABUF 1
28#define DRM_VMW_UNREF_DMABUF 2
Christopher Ferris525ce912017-07-26 13:12:53 -070029#define DRM_VMW_HANDLE_CLOSE 2
Christopher Ferris38062f92014-07-09 15:33:25 -070030#define DRM_VMW_CURSOR_BYPASS 3
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define DRM_VMW_CONTROL_STREAM 4
32#define DRM_VMW_CLAIM_STREAM 5
33#define DRM_VMW_UNREF_STREAM 6
Christopher Ferris38062f92014-07-09 15:33:25 -070034#define DRM_VMW_CREATE_CONTEXT 7
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define DRM_VMW_UNREF_CONTEXT 8
36#define DRM_VMW_CREATE_SURFACE 9
37#define DRM_VMW_UNREF_SURFACE 10
Christopher Ferris38062f92014-07-09 15:33:25 -070038#define DRM_VMW_REF_SURFACE 11
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define DRM_VMW_EXECBUF 12
40#define DRM_VMW_GET_3D_CAP 13
41#define DRM_VMW_FENCE_WAIT 14
Christopher Ferris38062f92014-07-09 15:33:25 -070042#define DRM_VMW_FENCE_SIGNALED 15
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define DRM_VMW_FENCE_UNREF 16
44#define DRM_VMW_FENCE_EVENT 17
45#define DRM_VMW_PRESENT 18
Christopher Ferris38062f92014-07-09 15:33:25 -070046#define DRM_VMW_PRESENT_READBACK 19
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define DRM_VMW_UPDATE_LAYOUT 20
Christopher Ferris38062f92014-07-09 15:33:25 -070048#define DRM_VMW_CREATE_SHADER 21
49#define DRM_VMW_UNREF_SHADER 22
Christopher Ferris38062f92014-07-09 15:33:25 -070050#define DRM_VMW_GB_SURFACE_CREATE 23
51#define DRM_VMW_GB_SURFACE_REF 24
52#define DRM_VMW_SYNCCPU 25
Christopher Ferris05d08e92016-02-04 13:16:38 -080053#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
Christopher Ferris05d08e92016-02-04 13:16:38 -080054#define DRM_VMW_PARAM_NUM_STREAMS 0
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
56#define DRM_VMW_PARAM_3D 2
Ben Cheng655a7c02013-10-16 16:09:24 -070057#define DRM_VMW_PARAM_HW_CAPS 3
Christopher Ferris05d08e92016-02-04 13:16:38 -080058#define DRM_VMW_PARAM_FIFO_CAPS 4
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define DRM_VMW_PARAM_MAX_FB_SIZE 5
60#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
Christopher Ferris38062f92014-07-09 15:33:25 -070061#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
Christopher Ferris05d08e92016-02-04 13:16:38 -080062#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
Christopher Ferris38062f92014-07-09 15:33:25 -070063#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
64#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
Christopher Ferris05d08e92016-02-04 13:16:38 -080065#define DRM_VMW_PARAM_SCREEN_TARGET 11
Christopher Ferris05d08e92016-02-04 13:16:38 -080066#define DRM_VMW_PARAM_DX 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070067enum drm_vmw_handle_type {
Tao Baod7db5942015-01-28 10:07:51 -080068 DRM_VMW_HANDLE_LEGACY = 0,
Tao Baod7db5942015-01-28 10:07:51 -080069 DRM_VMW_HANDLE_PRIME = 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070070};
Ben Cheng655a7c02013-10-16 16:09:24 -070071struct drm_vmw_getparam_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -070072 __u64 value;
73 __u32 param;
74 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070075};
76struct drm_vmw_context_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -070077 __s32 cid;
78 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070079};
80struct drm_vmw_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -070081 __u32 flags;
82 __u32 format;
83 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
Christopher Ferris106b3a82016-08-24 12:15:38 -070084 __u64 size_addr;
85 __s32 shareable;
86 __s32 scanout;
Ben Cheng655a7c02013-10-16 16:09:24 -070087};
Christopher Ferris106b3a82016-08-24 12:15:38 -070088struct drm_vmw_surface_arg {
89 __s32 sid;
Tao Baod7db5942015-01-28 10:07:51 -080090 enum drm_vmw_handle_type handle_type;
Ben Cheng655a7c02013-10-16 16:09:24 -070091};
92struct drm_vmw_size {
Christopher Ferris106b3a82016-08-24 12:15:38 -070093 __u32 width;
94 __u32 height;
95 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -070096 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070097};
98union drm_vmw_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -080099 struct drm_vmw_surface_arg rep;
100 struct drm_vmw_surface_create_req req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700101};
102union drm_vmw_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800103 struct drm_vmw_surface_create_req rep;
104 struct drm_vmw_surface_arg req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700105};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106#define DRM_VMW_EXECBUF_VERSION 2
Christopher Ferris1308ad32017-11-14 17:32:13 -0800107#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
108#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700109struct drm_vmw_execbuf_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700110 __u64 commands;
111 __u32 command_size;
112 __u32 throttle_us;
113 __u64 fence_rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700114 __u32 version;
115 __u32 flags;
116 __u32 context_handle;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800117 __s32 imported_fence_fd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700118};
Ben Cheng655a7c02013-10-16 16:09:24 -0700119struct drm_vmw_fence_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700120 __u32 handle;
121 __u32 mask;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700122 __u32 seqno;
123 __u32 passed_seqno;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800124 __s32 fd;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700125 __s32 error;
Ben Cheng655a7c02013-10-16 16:09:24 -0700126};
Ben Cheng655a7c02013-10-16 16:09:24 -0700127struct drm_vmw_alloc_dmabuf_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700128 __u32 size;
129 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700130};
Ben Cheng655a7c02013-10-16 16:09:24 -0700131struct drm_vmw_dmabuf_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700132 __u64 map_handle;
133 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700134 __u32 cur_gmr_id;
135 __u32 cur_gmr_offset;
136 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700137};
138union drm_vmw_alloc_dmabuf_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800139 struct drm_vmw_alloc_dmabuf_req req;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800140 struct drm_vmw_dmabuf_rep rep;
Ben Cheng655a7c02013-10-16 16:09:24 -0700141};
142struct drm_vmw_unref_dmabuf_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700143 __u32 handle;
144 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700145};
146struct drm_vmw_rect {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700147 __s32 x;
148 __s32 y;
149 __u32 w;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700150 __u32 h;
Ben Cheng655a7c02013-10-16 16:09:24 -0700151};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800152struct drm_vmw_control_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700153 __u32 stream_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700154 __u32 enabled;
155 __u32 flags;
156 __u32 color_key;
157 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700158 __u32 offset;
159 __s32 format;
160 __u32 size;
161 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700162 __u32 height;
163 __u32 pitch[3];
164 __u32 pad64;
Tao Baod7db5942015-01-28 10:07:51 -0800165 struct drm_vmw_rect src;
166 struct drm_vmw_rect dst;
Ben Cheng655a7c02013-10-16 16:09:24 -0700167};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800168#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700169#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
170struct drm_vmw_cursor_bypass_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700171 __u32 flags;
172 __u32 crtc_id;
173 __s32 xpos;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700174 __s32 ypos;
175 __s32 xhot;
176 __s32 yhot;
Ben Cheng655a7c02013-10-16 16:09:24 -0700177};
178struct drm_vmw_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700179 __u32 stream_id;
180 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700181};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700182struct drm_vmw_get_3d_cap_arg {
183 __u64 buffer;
184 __u32 max_size;
185 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700186};
Ben Cheng655a7c02013-10-16 16:09:24 -0700187#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800188#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700189#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
190struct drm_vmw_fence_wait_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700191 __u32 handle;
192 __s32 cookie_valid;
193 __u64 kernel_cookie;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700194 __u64 timeout_us;
195 __s32 lazy;
196 __s32 flags;
197 __s32 wait_options;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700198 __s32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700199};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800200struct drm_vmw_fence_signaled_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700201 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700202 __u32 flags;
203 __s32 signaled;
204 __u32 passed_seqno;
205 __u32 signaled_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700206 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700207};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800208struct drm_vmw_fence_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700209 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700210 __u32 pad64;
211};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800212#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700213struct drm_vmw_event_fence {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700214 struct drm_event base;
215 __u64 user_data;
216 __u32 tv_sec;
217 __u32 tv_usec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700218};
Ben Cheng655a7c02013-10-16 16:09:24 -0700219#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800220struct drm_vmw_fence_event_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700221 __u64 fence_rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700222 __u64 user_data;
223 __u32 handle;
224 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700225};
226struct drm_vmw_present_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700227 __u32 fb_id;
228 __u32 sid;
229 __s32 dest_x;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700230 __s32 dest_y;
231 __u64 clips_ptr;
232 __u32 num_clips;
233 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700234};
Ben Cheng655a7c02013-10-16 16:09:24 -0700235struct drm_vmw_present_readback_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700236 __u32 fb_id;
237 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700238 __u64 clips_ptr;
239 __u64 fence_rep;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800240};
Ben Cheng655a7c02013-10-16 16:09:24 -0700241struct drm_vmw_update_layout_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700242 __u32 num_outputs;
243 __u32 pad64;
244 __u64 rects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700245};
246enum drm_vmw_shader_type {
Tao Baod7db5942015-01-28 10:07:51 -0800247 drm_vmw_shader_type_vs = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800248 drm_vmw_shader_type_ps,
Christopher Ferris38062f92014-07-09 15:33:25 -0700249};
250struct drm_vmw_shader_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800251 enum drm_vmw_shader_type shader_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700252 __u32 size;
253 __u32 buffer_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700254 __u32 shader_handle;
255 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700256};
257struct drm_vmw_shader_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700258 __u32 handle;
259 __u32 pad64;
Christopher Ferris38062f92014-07-09 15:33:25 -0700260};
261enum drm_vmw_surface_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800262 drm_vmw_surface_flag_shareable = (1 << 0),
263 drm_vmw_surface_flag_scanout = (1 << 1),
Tao Baod7db5942015-01-28 10:07:51 -0800264 drm_vmw_surface_flag_create_buffer = (1 << 2)
Christopher Ferris38062f92014-07-09 15:33:25 -0700265};
266struct drm_vmw_gb_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700267 __u32 svga3d_flags;
268 __u32 format;
269 __u32 mip_levels;
Tao Baod7db5942015-01-28 10:07:51 -0800270 enum drm_vmw_surface_flags drm_surface_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700271 __u32 multisample_count;
272 __u32 autogen_filter;
273 __u32 buffer_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700274 __u32 array_size;
Tao Baod7db5942015-01-28 10:07:51 -0800275 struct drm_vmw_size base_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700276};
277struct drm_vmw_gb_surface_create_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700278 __u32 handle;
279 __u32 backup_size;
280 __u32 buffer_handle;
281 __u32 buffer_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700282 __u64 buffer_map_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700283};
Christopher Ferris38062f92014-07-09 15:33:25 -0700284union drm_vmw_gb_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800285 struct drm_vmw_gb_surface_create_rep rep;
286 struct drm_vmw_gb_surface_create_req req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700287};
Christopher Ferris38062f92014-07-09 15:33:25 -0700288struct drm_vmw_gb_surface_ref_rep {
Tao Baod7db5942015-01-28 10:07:51 -0800289 struct drm_vmw_gb_surface_create_req creq;
290 struct drm_vmw_gb_surface_create_rep crep;
Christopher Ferris38062f92014-07-09 15:33:25 -0700291};
Christopher Ferris38062f92014-07-09 15:33:25 -0700292union drm_vmw_gb_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800293 struct drm_vmw_gb_surface_ref_rep rep;
294 struct drm_vmw_surface_arg req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700295};
Christopher Ferris38062f92014-07-09 15:33:25 -0700296enum drm_vmw_synccpu_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800297 drm_vmw_synccpu_read = (1 << 0),
298 drm_vmw_synccpu_write = (1 << 1),
299 drm_vmw_synccpu_dontblock = (1 << 2),
Tao Baod7db5942015-01-28 10:07:51 -0800300 drm_vmw_synccpu_allow_cs = (1 << 3)
Christopher Ferris38062f92014-07-09 15:33:25 -0700301};
302enum drm_vmw_synccpu_op {
Tao Baod7db5942015-01-28 10:07:51 -0800303 drm_vmw_synccpu_grab,
Tao Baod7db5942015-01-28 10:07:51 -0800304 drm_vmw_synccpu_release
Christopher Ferris38062f92014-07-09 15:33:25 -0700305};
306struct drm_vmw_synccpu_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800307 enum drm_vmw_synccpu_op op;
Tao Baod7db5942015-01-28 10:07:51 -0800308 enum drm_vmw_synccpu_flags flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700309 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700310 __u32 pad64;
311};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800312enum drm_vmw_extended_context {
313 drm_vmw_context_legacy,
314 drm_vmw_context_dx
315};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800316union drm_vmw_extended_context_arg {
317 enum drm_vmw_extended_context req;
318 struct drm_vmw_context_arg rep;
319};
Christopher Ferris525ce912017-07-26 13:12:53 -0700320struct drm_vmw_handle_close_arg {
321 __u32 handle;
322 __u32 pad64;
323};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700324#ifdef __cplusplus
325#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700326#endif