blob: 618b6dca951ad2f6ea9a7854dd31793a1204f8ec [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __R128_DRM_H__
20#define __R128_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#ifndef __R128_SAREA_DEFINES__
Christopher Ferris05d08e92016-02-04 13:16:38 -080026#define __R128_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define R128_UPLOAD_CONTEXT 0x001
28#define R128_UPLOAD_SETUP 0x002
29#define R128_UPLOAD_TEX0 0x004
Christopher Ferris05d08e92016-02-04 13:16:38 -080030#define R128_UPLOAD_TEX1 0x008
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define R128_UPLOAD_TEX0IMAGES 0x010
32#define R128_UPLOAD_TEX1IMAGES 0x020
33#define R128_UPLOAD_CORE 0x040
Christopher Ferris05d08e92016-02-04 13:16:38 -080034#define R128_UPLOAD_MASKS 0x080
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define R128_UPLOAD_WINDOW 0x100
36#define R128_UPLOAD_CLIPRECTS 0x200
37#define R128_REQUIRE_QUIESCENCE 0x400
Christopher Ferris05d08e92016-02-04 13:16:38 -080038#define R128_UPLOAD_ALL 0x7ff
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define R128_FRONT 0x1
40#define R128_BACK 0x2
41#define R128_DEPTH 0x4
Christopher Ferris05d08e92016-02-04 13:16:38 -080042#define R128_POINTS 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define R128_LINES 0x2
44#define R128_LINE_STRIP 0x3
45#define R128_TRIANGLES 0x4
Christopher Ferris05d08e92016-02-04 13:16:38 -080046#define R128_TRIANGLE_FAN 0x5
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define R128_TRIANGLE_STRIP 0x6
48#define R128_BUFFER_SIZE 16384
49#define R128_INDEX_PRIM_OFFSET 20
Christopher Ferris05d08e92016-02-04 13:16:38 -080050#define R128_HOSTDATA_BLIT_OFFSET 32
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define R128_NR_SAREA_CLIPRECTS 12
52#define R128_LOCAL_TEX_HEAP 0
53#define R128_AGP_TEX_HEAP 1
Christopher Ferris05d08e92016-02-04 13:16:38 -080054#define R128_NR_TEX_HEAPS 2
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define R128_NR_TEX_REGIONS 64
56#define R128_LOG_TEX_GRANULARITY 16
57#define R128_NR_CONTEXT_REGS 12
Christopher Ferris05d08e92016-02-04 13:16:38 -080058#define R128_MAX_TEXTURE_LEVELS 11
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define R128_MAX_TEXTURE_UNITS 2
60#endif
61typedef struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 unsigned int dst_pitch_offset_c;
Tao Baod7db5942015-01-28 10:07:51 -080063 unsigned int dp_gui_master_cntl_c;
64 unsigned int sc_top_left_c;
65 unsigned int sc_bottom_right_c;
Christopher Ferris05d08e92016-02-04 13:16:38 -080066 unsigned int z_offset_c;
Tao Baod7db5942015-01-28 10:07:51 -080067 unsigned int z_pitch_c;
68 unsigned int z_sten_cntl_c;
69 unsigned int tex_cntl_c;
Christopher Ferris05d08e92016-02-04 13:16:38 -080070 unsigned int misc_3d_state_cntl_reg;
Tao Baod7db5942015-01-28 10:07:51 -080071 unsigned int texture_clr_cmp_clr_c;
72 unsigned int texture_clr_cmp_msk_c;
73 unsigned int fog_color_c;
Christopher Ferris05d08e92016-02-04 13:16:38 -080074 unsigned int tex_size_pitch_c;
Tao Baod7db5942015-01-28 10:07:51 -080075 unsigned int constant_color_c;
76 unsigned int pm4_vc_fpu_setup;
77 unsigned int setup_cntl;
Christopher Ferris05d08e92016-02-04 13:16:38 -080078 unsigned int dp_write_mask;
Tao Baod7db5942015-01-28 10:07:51 -080079 unsigned int sten_ref_mask_c;
80 unsigned int plane_3d_mask_c;
81 unsigned int window_xy_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080082 unsigned int scale_3d_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070083} drm_r128_context_regs_t;
84typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080085 unsigned int tex_cntl;
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 unsigned int tex_combine_cntl;
Tao Baod7db5942015-01-28 10:07:51 -080087 unsigned int tex_size_pitch;
88 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
89 unsigned int tex_border_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -080090} drm_r128_texture_regs_t;
Ben Cheng655a7c02013-10-16 16:09:24 -070091typedef struct drm_r128_sarea {
Tao Baod7db5942015-01-28 10:07:51 -080092 drm_r128_context_regs_t context_state;
93 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
Christopher Ferris05d08e92016-02-04 13:16:38 -080094 unsigned int dirty;
Tao Baod7db5942015-01-28 10:07:51 -080095 unsigned int vertsize;
96 unsigned int vc_format;
97 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
Christopher Ferris05d08e92016-02-04 13:16:38 -080098 unsigned int nbox;
Tao Baod7db5942015-01-28 10:07:51 -080099 unsigned int last_frame;
100 unsigned int last_dispatch;
101 struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800102 unsigned int tex_age[R128_NR_TEX_HEAPS];
Tao Baod7db5942015-01-28 10:07:51 -0800103 int ctx_owner;
104 int pfAllowPageFlip;
105 int pfCurrentPage;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106} drm_r128_sarea_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700107#define DRM_R128_INIT 0x00
108#define DRM_R128_CCE_START 0x01
109#define DRM_R128_CCE_STOP 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110#define DRM_R128_CCE_RESET 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700111#define DRM_R128_CCE_IDLE 0x04
112#define DRM_R128_RESET 0x06
113#define DRM_R128_SWAP 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114#define DRM_R128_CLEAR 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700115#define DRM_R128_VERTEX 0x09
116#define DRM_R128_INDICES 0x0a
117#define DRM_R128_BLIT 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118#define DRM_R128_DEPTH 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700119#define DRM_R128_STIPPLE 0x0d
120#define DRM_R128_INDIRECT 0x0f
121#define DRM_R128_FULLSCREEN 0x10
Christopher Ferris05d08e92016-02-04 13:16:38 -0800122#define DRM_R128_CLEAR2 0x11
Ben Cheng655a7c02013-10-16 16:09:24 -0700123#define DRM_R128_GETPARAM 0x12
124#define DRM_R128_FLIP 0x13
Tao Baod7db5942015-01-28 10:07:51 -0800125#define DRM_IOCTL_R128_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800126#define DRM_IOCTL_R128_CCE_START DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_START)
Tao Baod7db5942015-01-28 10:07:51 -0800127#define DRM_IOCTL_R128_CCE_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
128#define DRM_IOCTL_R128_CCE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
129#define DRM_IOCTL_R128_CCE_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800130#define DRM_IOCTL_R128_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_RESET)
Tao Baod7db5942015-01-28 10:07:51 -0800131#define DRM_IOCTL_R128_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_R128_SWAP)
132#define DRM_IOCTL_R128_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
133#define DRM_IOCTL_R128_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134#define DRM_IOCTL_R128_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
Tao Baod7db5942015-01-28 10:07:51 -0800135#define DRM_IOCTL_R128_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
136#define DRM_IOCTL_R128_DEPTH DRM_IOW(DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
137#define DRM_IOCTL_R128_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800138#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
Tao Baod7db5942015-01-28 10:07:51 -0800139#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
140#define DRM_IOCTL_R128_CLEAR2 DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
141#define DRM_IOCTL_R128_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800142#define DRM_IOCTL_R128_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_R128_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700143typedef struct drm_r128_init {
Tao Baod7db5942015-01-28 10:07:51 -0800144 enum {
145 R128_INIT_CCE = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800146 R128_CLEANUP_CCE = 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800147 } func;
148 unsigned long sarea_priv_offset;
149 int is_pci;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800150 int cce_mode;
Tao Baod7db5942015-01-28 10:07:51 -0800151 int cce_secure;
152 int ring_size;
153 int usec_timeout;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154 unsigned int fb_bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800155 unsigned int front_offset, front_pitch;
156 unsigned int back_offset, back_pitch;
157 unsigned int depth_bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800158 unsigned int depth_offset, depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800159 unsigned int span_offset;
160 unsigned long fb_offset;
161 unsigned long mmio_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800162 unsigned long ring_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800163 unsigned long ring_rptr_offset;
164 unsigned long buffers_offset;
165 unsigned long agp_textures_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800166} drm_r128_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700167typedef struct drm_r128_cce_stop {
Tao Baod7db5942015-01-28 10:07:51 -0800168 int flush;
169 int idle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800170} drm_r128_cce_stop_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700171typedef struct drm_r128_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800172 unsigned int flags;
173 unsigned int clear_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800174 unsigned int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800175 unsigned int color_mask;
176 unsigned int depth_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700177} drm_r128_clear_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800178typedef struct drm_r128_vertex {
Tao Baod7db5942015-01-28 10:07:51 -0800179 int prim;
180 int idx;
181 int count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800182 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700183} drm_r128_vertex_t;
184typedef struct drm_r128_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800185 int prim;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800186 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800187 int start;
188 int end;
189 int discard;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800190} drm_r128_indices_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700191typedef struct drm_r128_blit {
Tao Baod7db5942015-01-28 10:07:51 -0800192 int idx;
193 int pitch;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800194 int offset;
Tao Baod7db5942015-01-28 10:07:51 -0800195 int format;
196 unsigned short x, y;
197 unsigned short width, height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800198} drm_r128_blit_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700199typedef struct drm_r128_depth {
Tao Baod7db5942015-01-28 10:07:51 -0800200 enum {
201 R128_WRITE_SPAN = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800202 R128_WRITE_PIXELS = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800203 R128_READ_SPAN = 0x03,
204 R128_READ_PIXELS = 0x04
205 } func;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800206 int n;
Tao Baod7db5942015-01-28 10:07:51 -0800207 int __user * x;
208 int __user * y;
209 unsigned int __user * buffer;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800210 unsigned char __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700211} drm_r128_depth_t;
212typedef struct drm_r128_stipple {
Tao Baod7db5942015-01-28 10:07:51 -0800213 unsigned int __user * mask;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800214} drm_r128_stipple_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700215typedef struct drm_r128_indirect {
Tao Baod7db5942015-01-28 10:07:51 -0800216 int idx;
217 int start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800218 int end;
Tao Baod7db5942015-01-28 10:07:51 -0800219 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700220} drm_r128_indirect_t;
221typedef struct drm_r128_fullscreen {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800222 enum {
Tao Baod7db5942015-01-28 10:07:51 -0800223 R128_INIT_FULLSCREEN = 0x01,
224 R128_CLEANUP_FULLSCREEN = 0x02
225 } func;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800226} drm_r128_fullscreen_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700227#define R128_PARAM_IRQ_NR 1
228typedef struct drm_r128_getparam {
Tao Baod7db5942015-01-28 10:07:51 -0800229 int param;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800230 void __user * value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700231} drm_r128_getparam_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700232#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800233}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700234#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700235#endif