blob: 4959502f41ad13427c77a193f99d8abfea06604c [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MGA_DRM_H__
20#define __MGA_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#ifndef __MGA_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define __MGA_SAREA_DEFINES__
27#define MGA_F 0x1
28#define MGA_A 0x2
29#define MGA_S 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define MGA_T2 0x8
31#define MGA_WARP_TGZ 0
32#define MGA_WARP_TGZF (MGA_F)
33#define MGA_WARP_TGZA (MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080034#define MGA_WARP_TGZAF (MGA_F | MGA_A)
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define MGA_WARP_TGZS (MGA_S)
Tao Baod7db5942015-01-28 10:07:51 -080036#define MGA_WARP_TGZSF (MGA_S | MGA_F)
37#define MGA_WARP_TGZSA (MGA_S | MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080038#define MGA_WARP_TGZSAF (MGA_S | MGA_F | MGA_A)
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define MGA_WARP_T2GZ (MGA_T2)
Tao Baod7db5942015-01-28 10:07:51 -080040#define MGA_WARP_T2GZF (MGA_T2 | MGA_F)
41#define MGA_WARP_T2GZA (MGA_T2 | MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080042#define MGA_WARP_T2GZAF (MGA_T2 | MGA_A | MGA_F)
43#define MGA_WARP_T2GZS (MGA_T2 | MGA_S)
44#define MGA_WARP_T2GZSF (MGA_T2 | MGA_S | MGA_F)
45#define MGA_WARP_T2GZSA (MGA_T2 | MGA_S | MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080046#define MGA_WARP_T2GZSAF (MGA_T2 | MGA_S | MGA_F | MGA_A)
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define MGA_MAX_G200_PIPES 8
48#define MGA_MAX_G400_PIPES 16
49#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
Ben Cheng655a7c02013-10-16 16:09:24 -070050#define MGA_WARP_UCODE_SIZE 32768
51#define MGA_CARD_TYPE_G200 1
52#define MGA_CARD_TYPE_G400 2
53#define MGA_CARD_TYPE_G450 3
Ben Cheng655a7c02013-10-16 16:09:24 -070054#define MGA_CARD_TYPE_G550 4
55#define MGA_FRONT 0x1
56#define MGA_BACK 0x2
57#define MGA_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070058#define MGA_UPLOAD_CONTEXT 0x1
59#define MGA_UPLOAD_TEX0 0x2
60#define MGA_UPLOAD_TEX1 0x4
61#define MGA_UPLOAD_PIPE 0x8
Ben Cheng655a7c02013-10-16 16:09:24 -070062#define MGA_UPLOAD_TEX0IMAGE 0x10
63#define MGA_UPLOAD_TEX1IMAGE 0x20
64#define MGA_UPLOAD_2D 0x40
65#define MGA_WAIT_AGE 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -070066#define MGA_UPLOAD_CLIPRECTS 0x100
67#define MGA_BUFFER_SIZE (1 << 16)
68#define MGA_NUM_BUFFERS 128
69#define MGA_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -070070#define MGA_CARD_HEAP 0
71#define MGA_AGP_HEAP 1
72#define MGA_NR_TEX_HEAPS 2
73#define MGA_NR_TEX_REGIONS 16
Ben Cheng655a7c02013-10-16 16:09:24 -070074#define MGA_LOG_MIN_TEX_REGION_SIZE 16
75#define DRM_MGA_IDLE_RETRY 2048
76#endif
77typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080078 unsigned int dstorg;
79 unsigned int maccess;
80 unsigned int plnwt;
81 unsigned int dwgctl;
Tao Baod7db5942015-01-28 10:07:51 -080082 unsigned int alphactrl;
83 unsigned int fogcolor;
84 unsigned int wflag;
85 unsigned int tdualstage0;
Tao Baod7db5942015-01-28 10:07:51 -080086 unsigned int tdualstage1;
87 unsigned int fcol;
88 unsigned int stencil;
89 unsigned int stencilctl;
Ben Cheng655a7c02013-10-16 16:09:24 -070090} drm_mga_context_regs_t;
91typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080092 unsigned int pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -070093} drm_mga_server_regs_t;
Ben Cheng655a7c02013-10-16 16:09:24 -070094typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080095 unsigned int texctl;
96 unsigned int texctl2;
97 unsigned int texfilter;
Tao Baod7db5942015-01-28 10:07:51 -080098 unsigned int texbordercol;
99 unsigned int texorg;
100 unsigned int texwidth;
101 unsigned int texheight;
Tao Baod7db5942015-01-28 10:07:51 -0800102 unsigned int texorg1;
103 unsigned int texorg2;
104 unsigned int texorg3;
105 unsigned int texorg4;
Ben Cheng655a7c02013-10-16 16:09:24 -0700106} drm_mga_texture_regs_t;
107typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800108 unsigned int head;
109 unsigned int wrap;
Ben Cheng655a7c02013-10-16 16:09:24 -0700110} drm_mga_age_t;
111typedef struct _drm_mga_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800112 drm_mga_context_regs_t context_state;
113 drm_mga_server_regs_t server_state;
Tao Baod7db5942015-01-28 10:07:51 -0800114 drm_mga_texture_regs_t tex_state[2];
115 unsigned int warp_pipe;
116 unsigned int dirty;
117 unsigned int vertsize;
Tao Baod7db5942015-01-28 10:07:51 -0800118 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
119 unsigned int nbox;
120 unsigned int req_drawable;
121 unsigned int req_draw_buffer;
Tao Baod7db5942015-01-28 10:07:51 -0800122 unsigned int exported_drawable;
123 unsigned int exported_index;
124 unsigned int exported_stamp;
125 unsigned int exported_buffers;
Tao Baod7db5942015-01-28 10:07:51 -0800126 unsigned int exported_nfront;
127 unsigned int exported_nback;
128 int exported_back_x, exported_front_x, exported_w;
129 int exported_back_y, exported_front_y, exported_h;
Tao Baod7db5942015-01-28 10:07:51 -0800130 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
131 unsigned int status[4];
132 unsigned int last_wrap;
133 drm_mga_age_t last_frame;
Tao Baod7db5942015-01-28 10:07:51 -0800134 unsigned int last_enqueue;
135 unsigned int last_dispatch;
136 unsigned int last_quiescent;
137 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
Tao Baod7db5942015-01-28 10:07:51 -0800138 unsigned int texAge[MGA_NR_TEX_HEAPS];
139 int ctxOwner;
Ben Cheng655a7c02013-10-16 16:09:24 -0700140} drm_mga_sarea_t;
141#define DRM_MGA_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700142#define DRM_MGA_FLUSH 0x01
143#define DRM_MGA_RESET 0x02
144#define DRM_MGA_SWAP 0x03
145#define DRM_MGA_CLEAR 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700146#define DRM_MGA_VERTEX 0x05
147#define DRM_MGA_INDICES 0x06
148#define DRM_MGA_ILOAD 0x07
149#define DRM_MGA_BLIT 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700150#define DRM_MGA_GETPARAM 0x09
151#define DRM_MGA_SET_FENCE 0x0a
152#define DRM_MGA_WAIT_FENCE 0x0b
153#define DRM_MGA_DMA_BOOTSTRAP 0x0c
Tao Baod7db5942015-01-28 10:07:51 -0800154#define DRM_IOCTL_MGA_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
155#define DRM_IOCTL_MGA_FLUSH DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
156#define DRM_IOCTL_MGA_RESET DRM_IO(DRM_COMMAND_BASE + DRM_MGA_RESET)
157#define DRM_IOCTL_MGA_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_MGA_SWAP)
Tao Baod7db5942015-01-28 10:07:51 -0800158#define DRM_IOCTL_MGA_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
159#define DRM_IOCTL_MGA_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
160#define DRM_IOCTL_MGA_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
161#define DRM_IOCTL_MGA_ILOAD DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
Tao Baod7db5942015-01-28 10:07:51 -0800162#define DRM_IOCTL_MGA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700163#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
Tao Baod7db5942015-01-28 10:07:51 -0800164#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
Ben Cheng655a7c02013-10-16 16:09:24 -0700165#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
Ben Cheng655a7c02013-10-16 16:09:24 -0700166#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
167typedef struct _drm_mga_warp_index {
Tao Baod7db5942015-01-28 10:07:51 -0800168 int installed;
169 unsigned long phys_addr;
Tao Baod7db5942015-01-28 10:07:51 -0800170 int size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700171} drm_mga_warp_index_t;
172typedef struct drm_mga_init {
Tao Baod7db5942015-01-28 10:07:51 -0800173 enum {
Tao Baod7db5942015-01-28 10:07:51 -0800174 MGA_INIT_DMA = 0x01,
175 MGA_CLEANUP_DMA = 0x02
176 } func;
177 unsigned long sarea_priv_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800178 int chipset;
179 int sgram;
180 unsigned int maccess;
181 unsigned int fb_cpp;
Tao Baod7db5942015-01-28 10:07:51 -0800182 unsigned int front_offset, front_pitch;
183 unsigned int back_offset, back_pitch;
184 unsigned int depth_cpp;
185 unsigned int depth_offset, depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800186 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
187 unsigned int texture_size[MGA_NR_TEX_HEAPS];
188 unsigned long fb_offset;
189 unsigned long mmio_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800190 unsigned long status_offset;
191 unsigned long warp_offset;
192 unsigned long primary_offset;
193 unsigned long buffers_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700194} drm_mga_init_t;
195typedef struct drm_mga_dma_bootstrap {
Tao Baod7db5942015-01-28 10:07:51 -0800196 unsigned long texture_handle;
197 __u32 texture_size;
Tao Baod7db5942015-01-28 10:07:51 -0800198 __u32 primary_size;
199 __u32 secondary_bin_count;
200 __u32 secondary_bin_size;
201 __u32 agp_mode;
Tao Baod7db5942015-01-28 10:07:51 -0800202 __u8 agp_size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700203} drm_mga_dma_bootstrap_t;
204typedef struct drm_mga_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800205 unsigned int flags;
Tao Baod7db5942015-01-28 10:07:51 -0800206 unsigned int clear_color;
207 unsigned int clear_depth;
208 unsigned int color_mask;
209 unsigned int depth_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700210} drm_mga_clear_t;
211typedef struct drm_mga_vertex {
Tao Baod7db5942015-01-28 10:07:51 -0800212 int idx;
213 int used;
Tao Baod7db5942015-01-28 10:07:51 -0800214 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700215} drm_mga_vertex_t;
216typedef struct drm_mga_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800217 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800218 unsigned int start;
219 unsigned int end;
220 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700221} drm_mga_indices_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700222typedef struct drm_mga_iload {
Tao Baod7db5942015-01-28 10:07:51 -0800223 int idx;
224 unsigned int dstorg;
225 unsigned int length;
Ben Cheng655a7c02013-10-16 16:09:24 -0700226} drm_mga_iload_t;
227typedef struct _drm_mga_blit {
Tao Baod7db5942015-01-28 10:07:51 -0800228 unsigned int planemask;
229 unsigned int srcorg;
Tao Baod7db5942015-01-28 10:07:51 -0800230 unsigned int dstorg;
231 int src_pitch, dst_pitch;
232 int delta_sx, delta_sy;
233 int delta_dx, delta_dy;
Tao Baod7db5942015-01-28 10:07:51 -0800234 int height, ydir;
235 int source_pitch, dest_pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700236} drm_mga_blit_t;
237#define MGA_PARAM_IRQ_NR 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700238#define MGA_PARAM_CARD_TYPE 2
239typedef struct drm_mga_getparam {
Tao Baod7db5942015-01-28 10:07:51 -0800240 int param;
241 void __user * value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700242} drm_mga_getparam_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700243#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800244}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700245#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700246#endif