Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __MGA_DRM_H__ |
| 20 | #define __MGA_DRM_H__ |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 21 | #include "drm.h" |
| 22 | #ifdef __cplusplus |
Christopher Ferris | 48fe0ae | 2019-01-10 15:59:33 -0800 | [diff] [blame] | 23 | extern "C" { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 24 | #endif |
| 25 | #ifndef __MGA_SAREA_DEFINES__ |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 26 | #define __MGA_SAREA_DEFINES__ |
| 27 | #define MGA_F 0x1 |
| 28 | #define MGA_A 0x2 |
| 29 | #define MGA_S 0x4 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 30 | #define MGA_T2 0x8 |
| 31 | #define MGA_WARP_TGZ 0 |
| 32 | #define MGA_WARP_TGZF (MGA_F) |
| 33 | #define MGA_WARP_TGZA (MGA_A) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 34 | #define MGA_WARP_TGZAF (MGA_F | MGA_A) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 35 | #define MGA_WARP_TGZS (MGA_S) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 36 | #define MGA_WARP_TGZSF (MGA_S | MGA_F) |
| 37 | #define MGA_WARP_TGZSA (MGA_S | MGA_A) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 38 | #define MGA_WARP_TGZSAF (MGA_S | MGA_F | MGA_A) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 39 | #define MGA_WARP_T2GZ (MGA_T2) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 40 | #define MGA_WARP_T2GZF (MGA_T2 | MGA_F) |
| 41 | #define MGA_WARP_T2GZA (MGA_T2 | MGA_A) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 42 | #define MGA_WARP_T2GZAF (MGA_T2 | MGA_A | MGA_F) |
| 43 | #define MGA_WARP_T2GZS (MGA_T2 | MGA_S) |
| 44 | #define MGA_WARP_T2GZSF (MGA_T2 | MGA_S | MGA_F) |
| 45 | #define MGA_WARP_T2GZSA (MGA_T2 | MGA_S | MGA_A) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 46 | #define MGA_WARP_T2GZSAF (MGA_T2 | MGA_S | MGA_F | MGA_A) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 47 | #define MGA_MAX_G200_PIPES 8 |
| 48 | #define MGA_MAX_G400_PIPES 16 |
| 49 | #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 50 | #define MGA_WARP_UCODE_SIZE 32768 |
| 51 | #define MGA_CARD_TYPE_G200 1 |
| 52 | #define MGA_CARD_TYPE_G400 2 |
| 53 | #define MGA_CARD_TYPE_G450 3 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 54 | #define MGA_CARD_TYPE_G550 4 |
| 55 | #define MGA_FRONT 0x1 |
| 56 | #define MGA_BACK 0x2 |
| 57 | #define MGA_DEPTH 0x4 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 58 | #define MGA_UPLOAD_CONTEXT 0x1 |
| 59 | #define MGA_UPLOAD_TEX0 0x2 |
| 60 | #define MGA_UPLOAD_TEX1 0x4 |
| 61 | #define MGA_UPLOAD_PIPE 0x8 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 62 | #define MGA_UPLOAD_TEX0IMAGE 0x10 |
| 63 | #define MGA_UPLOAD_TEX1IMAGE 0x20 |
| 64 | #define MGA_UPLOAD_2D 0x40 |
| 65 | #define MGA_WAIT_AGE 0x80 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 66 | #define MGA_UPLOAD_CLIPRECTS 0x100 |
| 67 | #define MGA_BUFFER_SIZE (1 << 16) |
| 68 | #define MGA_NUM_BUFFERS 128 |
| 69 | #define MGA_NR_SAREA_CLIPRECTS 8 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 70 | #define MGA_CARD_HEAP 0 |
| 71 | #define MGA_AGP_HEAP 1 |
| 72 | #define MGA_NR_TEX_HEAPS 2 |
| 73 | #define MGA_NR_TEX_REGIONS 16 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 74 | #define MGA_LOG_MIN_TEX_REGION_SIZE 16 |
| 75 | #define DRM_MGA_IDLE_RETRY 2048 |
| 76 | #endif |
| 77 | typedef struct { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 78 | unsigned int dstorg; |
| 79 | unsigned int maccess; |
| 80 | unsigned int plnwt; |
| 81 | unsigned int dwgctl; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 82 | unsigned int alphactrl; |
| 83 | unsigned int fogcolor; |
| 84 | unsigned int wflag; |
| 85 | unsigned int tdualstage0; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 86 | unsigned int tdualstage1; |
| 87 | unsigned int fcol; |
| 88 | unsigned int stencil; |
| 89 | unsigned int stencilctl; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 90 | } drm_mga_context_regs_t; |
| 91 | typedef struct { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 92 | unsigned int pitch; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 93 | } drm_mga_server_regs_t; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 94 | typedef struct { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 95 | unsigned int texctl; |
| 96 | unsigned int texctl2; |
| 97 | unsigned int texfilter; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 98 | unsigned int texbordercol; |
| 99 | unsigned int texorg; |
| 100 | unsigned int texwidth; |
| 101 | unsigned int texheight; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 102 | unsigned int texorg1; |
| 103 | unsigned int texorg2; |
| 104 | unsigned int texorg3; |
| 105 | unsigned int texorg4; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 106 | } drm_mga_texture_regs_t; |
| 107 | typedef struct { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 108 | unsigned int head; |
| 109 | unsigned int wrap; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 110 | } drm_mga_age_t; |
| 111 | typedef struct _drm_mga_sarea { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 112 | drm_mga_context_regs_t context_state; |
| 113 | drm_mga_server_regs_t server_state; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 114 | drm_mga_texture_regs_t tex_state[2]; |
| 115 | unsigned int warp_pipe; |
| 116 | unsigned int dirty; |
| 117 | unsigned int vertsize; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 118 | struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; |
| 119 | unsigned int nbox; |
| 120 | unsigned int req_drawable; |
| 121 | unsigned int req_draw_buffer; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 122 | unsigned int exported_drawable; |
| 123 | unsigned int exported_index; |
| 124 | unsigned int exported_stamp; |
| 125 | unsigned int exported_buffers; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 126 | unsigned int exported_nfront; |
| 127 | unsigned int exported_nback; |
| 128 | int exported_back_x, exported_front_x, exported_w; |
| 129 | int exported_back_y, exported_front_y, exported_h; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 130 | struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; |
| 131 | unsigned int status[4]; |
| 132 | unsigned int last_wrap; |
| 133 | drm_mga_age_t last_frame; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 134 | unsigned int last_enqueue; |
| 135 | unsigned int last_dispatch; |
| 136 | unsigned int last_quiescent; |
| 137 | struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 138 | unsigned int texAge[MGA_NR_TEX_HEAPS]; |
| 139 | int ctxOwner; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 140 | } drm_mga_sarea_t; |
| 141 | #define DRM_MGA_INIT 0x00 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 142 | #define DRM_MGA_FLUSH 0x01 |
| 143 | #define DRM_MGA_RESET 0x02 |
| 144 | #define DRM_MGA_SWAP 0x03 |
| 145 | #define DRM_MGA_CLEAR 0x04 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 146 | #define DRM_MGA_VERTEX 0x05 |
| 147 | #define DRM_MGA_INDICES 0x06 |
| 148 | #define DRM_MGA_ILOAD 0x07 |
| 149 | #define DRM_MGA_BLIT 0x08 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 150 | #define DRM_MGA_GETPARAM 0x09 |
| 151 | #define DRM_MGA_SET_FENCE 0x0a |
| 152 | #define DRM_MGA_WAIT_FENCE 0x0b |
| 153 | #define DRM_MGA_DMA_BOOTSTRAP 0x0c |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 154 | #define DRM_IOCTL_MGA_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) |
| 155 | #define DRM_IOCTL_MGA_FLUSH DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) |
| 156 | #define DRM_IOCTL_MGA_RESET DRM_IO(DRM_COMMAND_BASE + DRM_MGA_RESET) |
| 157 | #define DRM_IOCTL_MGA_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_MGA_SWAP) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 158 | #define DRM_IOCTL_MGA_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) |
| 159 | #define DRM_IOCTL_MGA_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) |
| 160 | #define DRM_IOCTL_MGA_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) |
| 161 | #define DRM_IOCTL_MGA_ILOAD DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 162 | #define DRM_IOCTL_MGA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 163 | #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 164 | #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 165 | #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 166 | #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) |
| 167 | typedef struct _drm_mga_warp_index { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 168 | int installed; |
| 169 | unsigned long phys_addr; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 170 | int size; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 171 | } drm_mga_warp_index_t; |
| 172 | typedef struct drm_mga_init { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 173 | enum { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 174 | MGA_INIT_DMA = 0x01, |
| 175 | MGA_CLEANUP_DMA = 0x02 |
| 176 | } func; |
| 177 | unsigned long sarea_priv_offset; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 178 | int chipset; |
| 179 | int sgram; |
| 180 | unsigned int maccess; |
| 181 | unsigned int fb_cpp; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 182 | unsigned int front_offset, front_pitch; |
| 183 | unsigned int back_offset, back_pitch; |
| 184 | unsigned int depth_cpp; |
| 185 | unsigned int depth_offset, depth_pitch; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 186 | unsigned int texture_offset[MGA_NR_TEX_HEAPS]; |
| 187 | unsigned int texture_size[MGA_NR_TEX_HEAPS]; |
| 188 | unsigned long fb_offset; |
| 189 | unsigned long mmio_offset; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 190 | unsigned long status_offset; |
| 191 | unsigned long warp_offset; |
| 192 | unsigned long primary_offset; |
| 193 | unsigned long buffers_offset; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 194 | } drm_mga_init_t; |
| 195 | typedef struct drm_mga_dma_bootstrap { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 196 | unsigned long texture_handle; |
| 197 | __u32 texture_size; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 198 | __u32 primary_size; |
| 199 | __u32 secondary_bin_count; |
| 200 | __u32 secondary_bin_size; |
| 201 | __u32 agp_mode; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 202 | __u8 agp_size; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 203 | } drm_mga_dma_bootstrap_t; |
| 204 | typedef struct drm_mga_clear { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 205 | unsigned int flags; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 206 | unsigned int clear_color; |
| 207 | unsigned int clear_depth; |
| 208 | unsigned int color_mask; |
| 209 | unsigned int depth_mask; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 210 | } drm_mga_clear_t; |
| 211 | typedef struct drm_mga_vertex { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 212 | int idx; |
| 213 | int used; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 214 | int discard; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 215 | } drm_mga_vertex_t; |
| 216 | typedef struct drm_mga_indices { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 217 | int idx; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 218 | unsigned int start; |
| 219 | unsigned int end; |
| 220 | int discard; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 221 | } drm_mga_indices_t; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 222 | typedef struct drm_mga_iload { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 223 | int idx; |
| 224 | unsigned int dstorg; |
| 225 | unsigned int length; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 226 | } drm_mga_iload_t; |
| 227 | typedef struct _drm_mga_blit { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 228 | unsigned int planemask; |
| 229 | unsigned int srcorg; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 230 | unsigned int dstorg; |
| 231 | int src_pitch, dst_pitch; |
| 232 | int delta_sx, delta_sy; |
| 233 | int delta_dx, delta_dy; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 234 | int height, ydir; |
| 235 | int source_pitch, dest_pitch; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 236 | } drm_mga_blit_t; |
| 237 | #define MGA_PARAM_IRQ_NR 1 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 238 | #define MGA_PARAM_CARD_TYPE 2 |
| 239 | typedef struct drm_mga_getparam { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 240 | int param; |
| 241 | void __user * value; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 242 | } drm_mga_getparam_t; |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 243 | #ifdef __cplusplus |
Christopher Ferris | 48fe0ae | 2019-01-10 15:59:33 -0800 | [diff] [blame] | 244 | } |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 245 | #endif |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 246 | #endif |