blob: 38608ecd105456824f17df7e15c3a898dc7d6450 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MGA_DRM_H__
20#define __MGA_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -070023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#ifndef __MGA_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define __MGA_SAREA_DEFINES__
27#define MGA_F 0x1
Christopher Ferris106b3a82016-08-24 12:15:38 -070028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070029#define MGA_A 0x2
30#define MGA_S 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define MGA_T2 0x8
32#define MGA_WARP_TGZ 0
Christopher Ferris106b3a82016-08-24 12:15:38 -070033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070034#define MGA_WARP_TGZF (MGA_F)
35#define MGA_WARP_TGZA (MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080036#define MGA_WARP_TGZAF (MGA_F | MGA_A)
Ben Cheng655a7c02013-10-16 16:09:24 -070037#define MGA_WARP_TGZS (MGA_S)
Christopher Ferris106b3a82016-08-24 12:15:38 -070038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080039#define MGA_WARP_TGZSF (MGA_S | MGA_F)
40#define MGA_WARP_TGZSA (MGA_S | MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080041#define MGA_WARP_TGZSAF (MGA_S | MGA_F | MGA_A)
Ben Cheng655a7c02013-10-16 16:09:24 -070042#define MGA_WARP_T2GZ (MGA_T2)
Christopher Ferris106b3a82016-08-24 12:15:38 -070043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080044#define MGA_WARP_T2GZF (MGA_T2 | MGA_F)
45#define MGA_WARP_T2GZA (MGA_T2 | MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080046#define MGA_WARP_T2GZAF (MGA_T2 | MGA_A | MGA_F)
47#define MGA_WARP_T2GZS (MGA_T2 | MGA_S)
Christopher Ferris106b3a82016-08-24 12:15:38 -070048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080049#define MGA_WARP_T2GZSF (MGA_T2 | MGA_S | MGA_F)
50#define MGA_WARP_T2GZSA (MGA_T2 | MGA_S | MGA_A)
Tao Baod7db5942015-01-28 10:07:51 -080051#define MGA_WARP_T2GZSAF (MGA_T2 | MGA_S | MGA_F | MGA_A)
Ben Cheng655a7c02013-10-16 16:09:24 -070052#define MGA_MAX_G200_PIPES 8
Christopher Ferris106b3a82016-08-24 12:15:38 -070053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070054#define MGA_MAX_G400_PIPES 16
55#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
Ben Cheng655a7c02013-10-16 16:09:24 -070056#define MGA_WARP_UCODE_SIZE 32768
57#define MGA_CARD_TYPE_G200 1
Christopher Ferris106b3a82016-08-24 12:15:38 -070058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define MGA_CARD_TYPE_G400 2
60#define MGA_CARD_TYPE_G450 3
Ben Cheng655a7c02013-10-16 16:09:24 -070061#define MGA_CARD_TYPE_G550 4
62#define MGA_FRONT 0x1
Christopher Ferris106b3a82016-08-24 12:15:38 -070063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070064#define MGA_BACK 0x2
65#define MGA_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070066#define MGA_UPLOAD_CONTEXT 0x1
67#define MGA_UPLOAD_TEX0 0x2
Christopher Ferris106b3a82016-08-24 12:15:38 -070068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070069#define MGA_UPLOAD_TEX1 0x4
70#define MGA_UPLOAD_PIPE 0x8
Ben Cheng655a7c02013-10-16 16:09:24 -070071#define MGA_UPLOAD_TEX0IMAGE 0x10
72#define MGA_UPLOAD_TEX1IMAGE 0x20
Christopher Ferris106b3a82016-08-24 12:15:38 -070073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070074#define MGA_UPLOAD_2D 0x40
75#define MGA_WAIT_AGE 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -070076#define MGA_UPLOAD_CLIPRECTS 0x100
77#define MGA_BUFFER_SIZE (1 << 16)
Christopher Ferris106b3a82016-08-24 12:15:38 -070078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070079#define MGA_NUM_BUFFERS 128
80#define MGA_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -070081#define MGA_CARD_HEAP 0
82#define MGA_AGP_HEAP 1
Christopher Ferris106b3a82016-08-24 12:15:38 -070083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070084#define MGA_NR_TEX_HEAPS 2
85#define MGA_NR_TEX_REGIONS 16
Ben Cheng655a7c02013-10-16 16:09:24 -070086#define MGA_LOG_MIN_TEX_REGION_SIZE 16
87#define DRM_MGA_IDLE_RETRY 2048
Christopher Ferris106b3a82016-08-24 12:15:38 -070088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -070089#endif
90typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080091 unsigned int dstorg;
92 unsigned int maccess;
Christopher Ferris106b3a82016-08-24 12:15:38 -070093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080094 unsigned int plnwt;
95 unsigned int dwgctl;
Tao Baod7db5942015-01-28 10:07:51 -080096 unsigned int alphactrl;
97 unsigned int fogcolor;
Christopher Ferris106b3a82016-08-24 12:15:38 -070098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080099 unsigned int wflag;
100 unsigned int tdualstage0;
Tao Baod7db5942015-01-28 10:07:51 -0800101 unsigned int tdualstage1;
102 unsigned int fcol;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800104 unsigned int stencil;
105 unsigned int stencilctl;
Ben Cheng655a7c02013-10-16 16:09:24 -0700106} drm_mga_context_regs_t;
107typedef struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800109 unsigned int pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700110} drm_mga_server_regs_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700111typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800112 unsigned int texctl;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800114 unsigned int texctl2;
115 unsigned int texfilter;
Tao Baod7db5942015-01-28 10:07:51 -0800116 unsigned int texbordercol;
117 unsigned int texorg;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800119 unsigned int texwidth;
120 unsigned int texheight;
Tao Baod7db5942015-01-28 10:07:51 -0800121 unsigned int texorg1;
122 unsigned int texorg2;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800124 unsigned int texorg3;
125 unsigned int texorg4;
Ben Cheng655a7c02013-10-16 16:09:24 -0700126} drm_mga_texture_regs_t;
127typedef struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800129 unsigned int head;
130 unsigned int wrap;
Ben Cheng655a7c02013-10-16 16:09:24 -0700131} drm_mga_age_t;
132typedef struct _drm_mga_sarea {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800134 drm_mga_context_regs_t context_state;
135 drm_mga_server_regs_t server_state;
Tao Baod7db5942015-01-28 10:07:51 -0800136 drm_mga_texture_regs_t tex_state[2];
137 unsigned int warp_pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800139 unsigned int dirty;
140 unsigned int vertsize;
Tao Baod7db5942015-01-28 10:07:51 -0800141 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
142 unsigned int nbox;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800144 unsigned int req_drawable;
145 unsigned int req_draw_buffer;
Tao Baod7db5942015-01-28 10:07:51 -0800146 unsigned int exported_drawable;
147 unsigned int exported_index;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800149 unsigned int exported_stamp;
150 unsigned int exported_buffers;
Tao Baod7db5942015-01-28 10:07:51 -0800151 unsigned int exported_nfront;
152 unsigned int exported_nback;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800154 int exported_back_x, exported_front_x, exported_w;
155 int exported_back_y, exported_front_y, exported_h;
Tao Baod7db5942015-01-28 10:07:51 -0800156 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
157 unsigned int status[4];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800159 unsigned int last_wrap;
160 drm_mga_age_t last_frame;
Tao Baod7db5942015-01-28 10:07:51 -0800161 unsigned int last_enqueue;
162 unsigned int last_dispatch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800164 unsigned int last_quiescent;
165 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
Tao Baod7db5942015-01-28 10:07:51 -0800166 unsigned int texAge[MGA_NR_TEX_HEAPS];
167 int ctxOwner;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700169} drm_mga_sarea_t;
170#define DRM_MGA_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700171#define DRM_MGA_FLUSH 0x01
172#define DRM_MGA_RESET 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700174#define DRM_MGA_SWAP 0x03
175#define DRM_MGA_CLEAR 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700176#define DRM_MGA_VERTEX 0x05
177#define DRM_MGA_INDICES 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -0700178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700179#define DRM_MGA_ILOAD 0x07
180#define DRM_MGA_BLIT 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700181#define DRM_MGA_GETPARAM 0x09
182#define DRM_MGA_SET_FENCE 0x0a
Christopher Ferris106b3a82016-08-24 12:15:38 -0700183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700184#define DRM_MGA_WAIT_FENCE 0x0b
185#define DRM_MGA_DMA_BOOTSTRAP 0x0c
Tao Baod7db5942015-01-28 10:07:51 -0800186#define DRM_IOCTL_MGA_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
187#define DRM_IOCTL_MGA_FLUSH DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800189#define DRM_IOCTL_MGA_RESET DRM_IO(DRM_COMMAND_BASE + DRM_MGA_RESET)
190#define DRM_IOCTL_MGA_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_MGA_SWAP)
Tao Baod7db5942015-01-28 10:07:51 -0800191#define DRM_IOCTL_MGA_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
192#define DRM_IOCTL_MGA_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800194#define DRM_IOCTL_MGA_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
195#define DRM_IOCTL_MGA_ILOAD DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
Tao Baod7db5942015-01-28 10:07:51 -0800196#define DRM_IOCTL_MGA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700197#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800199#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
Ben Cheng655a7c02013-10-16 16:09:24 -0700200#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
Ben Cheng655a7c02013-10-16 16:09:24 -0700201#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
202typedef struct _drm_mga_warp_index {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800204 int installed;
205 unsigned long phys_addr;
Tao Baod7db5942015-01-28 10:07:51 -0800206 int size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700207} drm_mga_warp_index_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700209typedef struct drm_mga_init {
Tao Baod7db5942015-01-28 10:07:51 -0800210 enum {
Tao Baod7db5942015-01-28 10:07:51 -0800211 MGA_INIT_DMA = 0x01,
212 MGA_CLEANUP_DMA = 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800214 } func;
215 unsigned long sarea_priv_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800216 int chipset;
217 int sgram;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800219 unsigned int maccess;
220 unsigned int fb_cpp;
Tao Baod7db5942015-01-28 10:07:51 -0800221 unsigned int front_offset, front_pitch;
222 unsigned int back_offset, back_pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800224 unsigned int depth_cpp;
225 unsigned int depth_offset, depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800226 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
227 unsigned int texture_size[MGA_NR_TEX_HEAPS];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800229 unsigned long fb_offset;
230 unsigned long mmio_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800231 unsigned long status_offset;
232 unsigned long warp_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800234 unsigned long primary_offset;
235 unsigned long buffers_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700236} drm_mga_init_t;
237typedef struct drm_mga_dma_bootstrap {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800239 unsigned long texture_handle;
240 __u32 texture_size;
Tao Baod7db5942015-01-28 10:07:51 -0800241 __u32 primary_size;
242 __u32 secondary_bin_count;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800244 __u32 secondary_bin_size;
245 __u32 agp_mode;
Tao Baod7db5942015-01-28 10:07:51 -0800246 __u8 agp_size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700247} drm_mga_dma_bootstrap_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700249typedef struct drm_mga_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800250 unsigned int flags;
Tao Baod7db5942015-01-28 10:07:51 -0800251 unsigned int clear_color;
252 unsigned int clear_depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800254 unsigned int color_mask;
255 unsigned int depth_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700256} drm_mga_clear_t;
257typedef struct drm_mga_vertex {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800259 int idx;
260 int used;
Tao Baod7db5942015-01-28 10:07:51 -0800261 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700262} drm_mga_vertex_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700264typedef struct drm_mga_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800265 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800266 unsigned int start;
267 unsigned int end;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800269 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700270} drm_mga_indices_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700271typedef struct drm_mga_iload {
Tao Baod7db5942015-01-28 10:07:51 -0800272 int idx;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800274 unsigned int dstorg;
275 unsigned int length;
Ben Cheng655a7c02013-10-16 16:09:24 -0700276} drm_mga_iload_t;
277typedef struct _drm_mga_blit {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800279 unsigned int planemask;
280 unsigned int srcorg;
Tao Baod7db5942015-01-28 10:07:51 -0800281 unsigned int dstorg;
282 int src_pitch, dst_pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800284 int delta_sx, delta_sy;
285 int delta_dx, delta_dy;
Tao Baod7db5942015-01-28 10:07:51 -0800286 int height, ydir;
287 int source_pitch, dest_pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700289} drm_mga_blit_t;
290#define MGA_PARAM_IRQ_NR 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700291#define MGA_PARAM_CARD_TYPE 2
292typedef struct drm_mga_getparam {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800294 int param;
295 void __user * value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700296} drm_mga_getparam_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700297#ifdef __cplusplus
298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
299#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700300#endif