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gerrit.omnirom.org / android_bionic / 65b47c9fe08e183987a9857e3e3b5d66a63d6936 / . / libc / kernel / uapi / linux / pci_regs.h
blob: 250a3fc8e95109f030a87ccb575ed8122b24f940 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef LINUX_PCI_REGS_H
20#define LINUX_PCI_REGS_H
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]21#define PCI_CFG_SPACE_SIZE 256
22#define PCI_CFG_SPACE_EXP_SIZE 4096
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]24#define PCI_STD_HEADER_SIZEOF 64
25#define PCI_VENDOR_ID 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26#define PCI_DEVICE_ID 0x02
27#define PCI_COMMAND 0x04
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define PCI_COMMAND_IO 0x1
30#define PCI_COMMAND_MEMORY 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31#define PCI_COMMAND_MASTER 0x4
32#define PCI_COMMAND_SPECIAL 0x8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define PCI_COMMAND_INVALIDATE 0x10
35#define PCI_COMMAND_VGA_PALETTE 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36#define PCI_COMMAND_PARITY 0x40
37#define PCI_COMMAND_WAIT 0x80
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define PCI_COMMAND_SERR 0x100
40#define PCI_COMMAND_FAST_BACK 0x200
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41#define PCI_COMMAND_INTX_DISABLE 0x400
42#define PCI_STATUS 0x06
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44#define PCI_STATUS_INTERRUPT 0x08
45#define PCI_STATUS_CAP_LIST 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46#define PCI_STATUS_66MHZ 0x20
47#define PCI_STATUS_UDF 0x40
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49#define PCI_STATUS_FAST_BACK 0x80
50#define PCI_STATUS_PARITY 0x100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51#define PCI_STATUS_DEVSEL_MASK 0x600
52#define PCI_STATUS_DEVSEL_FAST 0x000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define PCI_STATUS_DEVSEL_MEDIUM 0x200
55#define PCI_STATUS_DEVSEL_SLOW 0x400
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]56#define PCI_STATUS_SIG_TARGET_ABORT 0x800
57#define PCI_STATUS_REC_TARGET_ABORT 0x1000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59#define PCI_STATUS_REC_MASTER_ABORT 0x2000
60#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]61#define PCI_STATUS_DETECTED_PARITY 0x8000
62#define PCI_CLASS_REVISION 0x08
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64#define PCI_REVISION_ID 0x08
65#define PCI_CLASS_PROG 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66#define PCI_CLASS_DEVICE 0x0a
67#define PCI_CACHE_LINE_SIZE 0x0c
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define PCI_LATENCY_TIMER 0x0d
70#define PCI_HEADER_TYPE 0x0e
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]71#define PCI_HEADER_TYPE_NORMAL 0
72#define PCI_HEADER_TYPE_BRIDGE 1
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define PCI_HEADER_TYPE_CARDBUS 2
75#define PCI_BIST 0x0f
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]76#define PCI_BIST_CODE_MASK 0x0f
77#define PCI_BIST_START 0x40
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79#define PCI_BIST_CAPABLE 0x80
80#define PCI_BASE_ADDRESS_0 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]81#define PCI_BASE_ADDRESS_1 0x14
82#define PCI_BASE_ADDRESS_2 0x18
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define PCI_BASE_ADDRESS_3 0x1c
85#define PCI_BASE_ADDRESS_4 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]86#define PCI_BASE_ADDRESS_5 0x24
87#define PCI_BASE_ADDRESS_SPACE 0x01
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define PCI_BASE_ADDRESS_SPACE_IO 0x01
90#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]91#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
92#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
95#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]96#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
97#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
100#define PCI_CARDBUS_CIS 0x28
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]101#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
102#define PCI_SUBSYSTEM_ID 0x2e
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104#define PCI_ROM_ADDRESS 0x30
105#define PCI_ROM_ADDRESS_ENABLE 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]106#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
107#define PCI_CAPABILITY_LIST 0x34
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109#define PCI_INTERRUPT_LINE 0x3c
110#define PCI_INTERRUPT_PIN 0x3d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]111#define PCI_MIN_GNT 0x3e
112#define PCI_MAX_LAT 0x3f
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114#define PCI_PRIMARY_BUS 0x18
115#define PCI_SECONDARY_BUS 0x19
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]116#define PCI_SUBORDINATE_BUS 0x1a
117#define PCI_SEC_LATENCY_TIMER 0x1b
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119#define PCI_IO_BASE 0x1c
120#define PCI_IO_LIMIT 0x1d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]121#define PCI_IO_RANGE_TYPE_MASK 0x0fUL
122#define PCI_IO_RANGE_TYPE_16 0x00
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define PCI_IO_RANGE_TYPE_32 0x01
125#define PCI_IO_RANGE_MASK (~0x0fUL)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126#define PCI_IO_1K_RANGE_MASK (~0x03UL)
127#define PCI_SEC_STATUS 0x1e
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define PCI_MEMORY_BASE 0x20
130#define PCI_MEMORY_LIMIT 0x22
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
132#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define PCI_PREF_MEMORY_BASE 0x24
135#define PCI_PREF_MEMORY_LIMIT 0x26
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]136#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
137#define PCI_PREF_RANGE_TYPE_32 0x00
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define PCI_PREF_RANGE_TYPE_64 0x01
140#define PCI_PREF_RANGE_MASK (~0x0fUL)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141#define PCI_PREF_BASE_UPPER32 0x28
142#define PCI_PREF_LIMIT_UPPER32 0x2c
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define PCI_IO_BASE_UPPER16 0x30
145#define PCI_IO_LIMIT_UPPER16 0x32
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]146#define PCI_ROM_ADDRESS1 0x38
147#define PCI_BRIDGE_CONTROL 0x3e
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define PCI_BRIDGE_CTL_PARITY 0x01
150#define PCI_BRIDGE_CTL_SERR 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]151#define PCI_BRIDGE_CTL_ISA 0x04
152#define PCI_BRIDGE_CTL_VGA 0x08
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
155#define PCI_BRIDGE_CTL_BUS_RESET 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]156#define PCI_BRIDGE_CTL_FAST_BACK 0x80
157#define PCI_CB_CAPABILITY_LIST 0x14
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159#define PCI_CB_SEC_STATUS 0x16
160#define PCI_CB_PRIMARY_BUS 0x18
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]161#define PCI_CB_CARD_BUS 0x19
162#define PCI_CB_SUBORDINATE_BUS 0x1a
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164#define PCI_CB_LATENCY_TIMER 0x1b
165#define PCI_CB_MEMORY_BASE_0 0x1c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]166#define PCI_CB_MEMORY_LIMIT_0 0x20
167#define PCI_CB_MEMORY_BASE_1 0x24
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169#define PCI_CB_MEMORY_LIMIT_1 0x28
170#define PCI_CB_IO_BASE_0 0x2c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]171#define PCI_CB_IO_BASE_0_HI 0x2e
172#define PCI_CB_IO_LIMIT_0 0x30
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174#define PCI_CB_IO_LIMIT_0_HI 0x32
175#define PCI_CB_IO_BASE_1 0x34
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]176#define PCI_CB_IO_BASE_1_HI 0x36
177#define PCI_CB_IO_LIMIT_1 0x38
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define PCI_CB_IO_LIMIT_1_HI 0x3a
180#define PCI_CB_IO_RANGE_MASK (~0x03UL)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181#define PCI_CB_BRIDGE_CONTROL 0x3e
182#define PCI_CB_BRIDGE_CTL_PARITY 0x01
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define PCI_CB_BRIDGE_CTL_SERR 0x02
185#define PCI_CB_BRIDGE_CTL_ISA 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]186#define PCI_CB_BRIDGE_CTL_VGA 0x08
187#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
190#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]191#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
192#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
195#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]196#define PCI_CB_SUBSYSTEM_ID 0x42
197#define PCI_CB_LEGACY_MODE_BASE 0x44
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define PCI_CAP_LIST_ID 0
200#define PCI_CAP_ID_PM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]201#define PCI_CAP_ID_AGP 0x02
202#define PCI_CAP_ID_VPD 0x03
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define PCI_CAP_ID_SLOTID 0x04
205#define PCI_CAP_ID_MSI 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]206#define PCI_CAP_ID_CHSWP 0x06
207#define PCI_CAP_ID_PCIX 0x07
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209#define PCI_CAP_ID_HT 0x08
210#define PCI_CAP_ID_VNDR 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]211#define PCI_CAP_ID_DBG 0x0A
212#define PCI_CAP_ID_CCRC 0x0B
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define PCI_CAP_ID_SHPC 0x0C
215#define PCI_CAP_ID_SSVID 0x0D
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216#define PCI_CAP_ID_AGP3 0x0E
217#define PCI_CAP_ID_SECDEV 0x0F
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define PCI_CAP_ID_EXP 0x10
220#define PCI_CAP_ID_MSIX 0x11
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]221#define PCI_CAP_ID_SATA 0x12
222#define PCI_CAP_ID_AF 0x13
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]224#define PCI_CAP_ID_EA 0x14
225#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]226#define PCI_CAP_LIST_NEXT 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227#define PCI_CAP_FLAGS 2
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229#define PCI_CAP_SIZEOF 4
230#define PCI_PM_PMC 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]231#define PCI_PM_CAP_VER_MASK 0x0007
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]232#define PCI_PM_CAP_PME_CLOCK 0x0008
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]234#define PCI_PM_CAP_RESERVED 0x0010
235#define PCI_PM_CAP_DSI 0x0020
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]236#define PCI_PM_CAP_AUX_POWER 0x01C0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]237#define PCI_PM_CAP_D1 0x0200
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]239#define PCI_PM_CAP_D2 0x0400
240#define PCI_PM_CAP_PME 0x0800
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]241#define PCI_PM_CAP_PME_MASK 0xF800
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]242#define PCI_PM_CAP_PME_D0 0x0800
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]244#define PCI_PM_CAP_PME_D1 0x1000
245#define PCI_PM_CAP_PME_D2 0x2000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]246#define PCI_PM_CAP_PME_D3 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]247#define PCI_PM_CAP_PME_D3cold 0x8000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249#define PCI_PM_CAP_PME_SHIFT 11
250#define PCI_PM_CTRL 4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]251#define PCI_PM_CTRL_STATE_MASK 0x0003
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]252#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254#define PCI_PM_CTRL_PME_ENABLE 0x0100
255#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]256#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]257#define PCI_PM_CTRL_PME_STATUS 0x8000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259#define PCI_PM_PPB_EXTENSIONS 6
260#define PCI_PM_PPB_B2_B3 0x40
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]261#define PCI_PM_BPCC_ENABLE 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]262#define PCI_PM_DATA_REGISTER 7
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264#define PCI_PM_SIZEOF 8
265#define PCI_AGP_VERSION 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]266#define PCI_AGP_RFU 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267#define PCI_AGP_STATUS 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]269#define PCI_AGP_STATUS_RQ_MASK 0xff000000
270#define PCI_AGP_STATUS_SBA 0x0200
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]271#define PCI_AGP_STATUS_64BIT 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]272#define PCI_AGP_STATUS_FW 0x0010
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274#define PCI_AGP_STATUS_RATE4 0x0004
275#define PCI_AGP_STATUS_RATE2 0x0002
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]276#define PCI_AGP_STATUS_RATE1 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]277#define PCI_AGP_COMMAND 8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]279#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
280#define PCI_AGP_COMMAND_SBA 0x0200
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]281#define PCI_AGP_COMMAND_AGP 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]282#define PCI_AGP_COMMAND_64BIT 0x0020
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284#define PCI_AGP_COMMAND_FW 0x0010
285#define PCI_AGP_COMMAND_RATE4 0x0004
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]286#define PCI_AGP_COMMAND_RATE2 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]287#define PCI_AGP_COMMAND_RATE1 0x0001
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]289#define PCI_AGP_SIZEOF 12
290#define PCI_VPD_ADDR 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]291#define PCI_VPD_ADDR_MASK 0x7fff
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]292#define PCI_VPD_ADDR_F 0x8000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]294#define PCI_VPD_DATA 4
295#define PCI_CAP_VPD_SIZEOF 8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]296#define PCI_SID_ESR 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]297#define PCI_SID_ESR_NSLOTS 0x1f
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299#define PCI_SID_ESR_FIC 0x20
300#define PCI_SID_CHASSIS_NR 3
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]301#define PCI_MSI_FLAGS 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302#define PCI_MSI_FLAGS_ENABLE 0x0001
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304#define PCI_MSI_FLAGS_QMASK 0x000e
305#define PCI_MSI_FLAGS_QSIZE 0x0070
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]306#define PCI_MSI_FLAGS_64BIT 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]307#define PCI_MSI_FLAGS_MASKBIT 0x0100
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]309#define PCI_MSI_RFU 3
310#define PCI_MSI_ADDRESS_LO 4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]311#define PCI_MSI_ADDRESS_HI 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]312#define PCI_MSI_DATA_32 8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]314#define PCI_MSI_MASK_32 12
315#define PCI_MSI_PENDING_32 16
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]316#define PCI_MSI_DATA_64 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]317#define PCI_MSI_MASK_64 16
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319#define PCI_MSI_PENDING_64 20
320#define PCI_MSIX_FLAGS 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]321#define PCI_MSIX_FLAGS_QSIZE 0x07FF
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]322#define PCI_MSIX_FLAGS_MASKALL 0x4000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]324#define PCI_MSIX_FLAGS_ENABLE 0x8000
325#define PCI_MSIX_TABLE 4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]326#define PCI_MSIX_TABLE_BIR 0x00000007
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]327#define PCI_MSIX_TABLE_OFFSET 0xfffffff8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]329#define PCI_MSIX_PBA 8
330#define PCI_MSIX_PBA_BIR 0x00000007
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]331#define PCI_MSIX_PBA_OFFSET 0xfffffff8
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]332#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]334#define PCI_CAP_MSIX_SIZEOF 12
335#define PCI_MSIX_ENTRY_SIZE 16
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]336#define PCI_MSIX_ENTRY_LOWER_ADDR 0
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]337#define PCI_MSIX_ENTRY_UPPER_ADDR 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]339#define PCI_MSIX_ENTRY_DATA 8
340#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]341#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]342#define PCI_CHSWP_CSR 2
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]344#define PCI_CHSWP_DHA 0x01
345#define PCI_CHSWP_EIM 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]346#define PCI_CHSWP_PIE 0x04
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]347#define PCI_CHSWP_LOO 0x08
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]349#define PCI_CHSWP_PI 0x30
350#define PCI_CHSWP_EXT 0x40
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]351#define PCI_CHSWP_INS 0x80
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]352#define PCI_AF_LENGTH 2
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]354#define PCI_AF_CAP 3
355#define PCI_AF_CAP_TP 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]356#define PCI_AF_CAP_FLR 0x02
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]357#define PCI_AF_CTRL 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]359#define PCI_AF_CTRL_FLR 0x01
360#define PCI_AF_STATUS 5
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]361#define PCI_AF_STATUS_TP 0x01
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]362#define PCI_CAP_AF_SIZEOF 6
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]364#define PCI_EA_NUM_ENT 2
365#define PCI_EA_NUM_ENT_MASK 0x3f
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]366#define PCI_EA_FIRST_ENT 4
367#define PCI_EA_FIRST_ENT_BRIDGE 8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]369#define PCI_EA_ES 0x00000007
370#define PCI_EA_BEI 0x000000f0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]371#define PCI_EA_BEI_BAR0 0
372#define PCI_EA_BEI_BAR5 5
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]374#define PCI_EA_BEI_BRIDGE 6
375#define PCI_EA_BEI_ENI 7
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]376#define PCI_EA_BEI_ROM 8
377#define PCI_EA_BEI_VF_BAR0 9
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]379#define PCI_EA_BEI_VF_BAR5 14
380#define PCI_EA_BEI_RESERVED 15
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]381#define PCI_EA_PP 0x0000ff00
382#define PCI_EA_SP 0x00ff0000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]384#define PCI_EA_P_MEM 0x00
385#define PCI_EA_P_MEM_PREFETCH 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]386#define PCI_EA_P_IO 0x02
387#define PCI_EA_P_VF_MEM_PREFETCH 0x03
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]389#define PCI_EA_P_VF_MEM 0x04
390#define PCI_EA_P_BRIDGE_MEM 0x05
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]391#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06
392#define PCI_EA_P_BRIDGE_IO 0x07
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]394#define PCI_EA_P_MEM_RESERVED 0xfd
395#define PCI_EA_P_IO_RESERVED 0xfe
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]396#define PCI_EA_P_UNAVAILABLE 0xff
397#define PCI_EA_WRITABLE 0x40000000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]399#define PCI_EA_ENABLE 0x80000000
400#define PCI_EA_BASE 4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]401#define PCI_EA_MAX_OFFSET 8
402#define PCI_EA_IS_64 0x00000002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]404#define PCI_EA_FIELD_MASK 0xfffffffc
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]405#define PCI_X_CMD 2
406#define PCI_X_CMD_DPERR_E 0x0001
407#define PCI_X_CMD_ERO 0x0002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]409#define PCI_X_CMD_READ_512 0x0000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]410#define PCI_X_CMD_READ_1K 0x0004
411#define PCI_X_CMD_READ_2K 0x0008
412#define PCI_X_CMD_READ_4K 0x000c
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]414#define PCI_X_CMD_MAX_READ 0x000c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]415#define PCI_X_CMD_SPLIT_1 0x0000
416#define PCI_X_CMD_SPLIT_2 0x0010
417#define PCI_X_CMD_SPLIT_3 0x0020
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]419#define PCI_X_CMD_SPLIT_4 0x0030
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]420#define PCI_X_CMD_SPLIT_8 0x0040
421#define PCI_X_CMD_SPLIT_12 0x0050
422#define PCI_X_CMD_SPLIT_16 0x0060
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]424#define PCI_X_CMD_SPLIT_32 0x0070
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]425#define PCI_X_CMD_MAX_SPLIT 0x0070
426#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
427#define PCI_X_STATUS 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]429#define PCI_X_STATUS_DEVFN 0x000000ff
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]430#define PCI_X_STATUS_BUS 0x0000ff00
431#define PCI_X_STATUS_64BIT 0x00010000
432#define PCI_X_STATUS_133MHZ 0x00020000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]434#define PCI_X_STATUS_SPL_DISC 0x00040000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]435#define PCI_X_STATUS_UNX_SPL 0x00080000
436#define PCI_X_STATUS_COMPLEX 0x00100000
437#define PCI_X_STATUS_MAX_READ 0x00600000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]439#define PCI_X_STATUS_MAX_SPLIT 0x03800000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]440#define PCI_X_STATUS_MAX_CUM 0x1c000000
441#define PCI_X_STATUS_SPL_ERR 0x20000000
442#define PCI_X_STATUS_266MHZ 0x40000000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]444#define PCI_X_STATUS_533MHZ 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]445#define PCI_X_ECC_CSR 8
446#define PCI_CAP_PCIX_SIZEOF_V0 8
447#define PCI_CAP_PCIX_SIZEOF_V1 24
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]449#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]450#define PCI_X_BRIDGE_SSTATUS 2
451#define PCI_X_SSTATUS_64BIT 0x0001
452#define PCI_X_SSTATUS_133MHZ 0x0002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]454#define PCI_X_SSTATUS_FREQ 0x03c0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]455#define PCI_X_SSTATUS_VERS 0x3000
456#define PCI_X_SSTATUS_V1 0x1000
457#define PCI_X_SSTATUS_V2 0x2000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]459#define PCI_X_SSTATUS_266MHZ 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]460#define PCI_X_SSTATUS_533MHZ 0x8000
461#define PCI_X_BRIDGE_STATUS 4
462#define PCI_SSVID_VENDOR_ID 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]464#define PCI_SSVID_DEVICE_ID 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]465#define PCI_EXP_FLAGS 2
466#define PCI_EXP_FLAGS_VERS 0x000f
467#define PCI_EXP_FLAGS_TYPE 0x00f0
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]469#define PCI_EXP_TYPE_ENDPOINT 0x0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]470#define PCI_EXP_TYPE_LEG_END 0x1
471#define PCI_EXP_TYPE_ROOT_PORT 0x4
472#define PCI_EXP_TYPE_UPSTREAM 0x5
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]474#define PCI_EXP_TYPE_DOWNSTREAM 0x6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]475#define PCI_EXP_TYPE_PCI_BRIDGE 0x7
476#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8
477#define PCI_EXP_TYPE_RC_END 0x9
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]479#define PCI_EXP_TYPE_RC_EC 0xa
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]480#define PCI_EXP_FLAGS_SLOT 0x0100
481#define PCI_EXP_FLAGS_IRQ 0x3e00
482#define PCI_EXP_DEVCAP 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]484#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]485#define PCI_EXP_DEVCAP_PHANTOM 0x00000018
486#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020
487#define PCI_EXP_DEVCAP_L0S 0x000001c0
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]489#define PCI_EXP_DEVCAP_L1 0x00000e00
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]490#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000
491#define PCI_EXP_DEVCAP_ATN_IND 0x00002000
492#define PCI_EXP_DEVCAP_PWR_IND 0x00004000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]494#define PCI_EXP_DEVCAP_RBER 0x00008000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]495#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000
496#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]497#define PCI_EXP_DEVCAP_FLR 0x10000000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]499#define PCI_EXP_DEVCTL 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]500#define PCI_EXP_DEVCTL_CERE 0x0001
501#define PCI_EXP_DEVCTL_NFERE 0x0002
502#define PCI_EXP_DEVCTL_FERE 0x0004
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]504#define PCI_EXP_DEVCTL_URRE 0x0008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]505#define PCI_EXP_DEVCTL_RELAX_EN 0x0010
506#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
507#define PCI_EXP_DEVCTL_EXT_TAG 0x0100
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]509#define PCI_EXP_DEVCTL_PHANTOM 0x0200
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]510#define PCI_EXP_DEVCTL_AUX_PME 0x0400
511#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
512#define PCI_EXP_DEVCTL_READRQ 0x7000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]514#define PCI_EXP_DEVCTL_READRQ_128B 0x0000
515#define PCI_EXP_DEVCTL_READRQ_256B 0x1000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]516#define PCI_EXP_DEVCTL_READRQ_512B 0x2000
517#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]519#define PCI_EXP_DEVCTL_BCR_FLR 0x8000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]520#define PCI_EXP_DEVSTA 10
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]521#define PCI_EXP_DEVSTA_CED 0x0001
522#define PCI_EXP_DEVSTA_NFED 0x0002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]524#define PCI_EXP_DEVSTA_FED 0x0004
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]525#define PCI_EXP_DEVSTA_URD 0x0008
526#define PCI_EXP_DEVSTA_AUXPD 0x0010
527#define PCI_EXP_DEVSTA_TRPND 0x0020
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]529#define PCI_EXP_LNKCAP 12
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]530#define PCI_EXP_LNKCAP_SLS 0x0000000f
531#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
532#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]534#define PCI_EXP_LNKCAP_MLW 0x000003f0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]535#define PCI_EXP_LNKCAP_ASPMS 0x00000c00
536#define PCI_EXP_LNKCAP_L0SEL 0x00007000
537#define PCI_EXP_LNKCAP_L1EL 0x00038000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]539#define PCI_EXP_LNKCAP_CLKPM 0x00040000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]540#define PCI_EXP_LNKCAP_SDERC 0x00080000
541#define PCI_EXP_LNKCAP_DLLLARC 0x00100000
542#define PCI_EXP_LNKCAP_LBNC 0x00200000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]544#define PCI_EXP_LNKCAP_PN 0xff000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]545#define PCI_EXP_LNKCTL 16
546#define PCI_EXP_LNKCTL_ASPMC 0x0003
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]547#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]549#define PCI_EXP_LNKCTL_ASPM_L1 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]550#define PCI_EXP_LNKCTL_RCB 0x0008
551#define PCI_EXP_LNKCTL_LD 0x0010
552#define PCI_EXP_LNKCTL_RL 0x0020
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]554#define PCI_EXP_LNKCTL_CCC 0x0040
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]555#define PCI_EXP_LNKCTL_ES 0x0080
556#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100
557#define PCI_EXP_LNKCTL_HAWD 0x0200
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]559#define PCI_EXP_LNKCTL_LBMIE 0x0400
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]560#define PCI_EXP_LNKCTL_LABIE 0x0800
561#define PCI_EXP_LNKSTA 18
562#define PCI_EXP_LNKSTA_CLS 0x000f
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]564#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]565#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002
566#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]567#define PCI_EXP_LNKSTA_NLW 0x03f0
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]569#define PCI_EXP_LNKSTA_NLW_X1 0x0010
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]570#define PCI_EXP_LNKSTA_NLW_X2 0x0020
571#define PCI_EXP_LNKSTA_NLW_X4 0x0040
572#define PCI_EXP_LNKSTA_NLW_X8 0x0080
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]574#define PCI_EXP_LNKSTA_NLW_SHIFT 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]575#define PCI_EXP_LNKSTA_LT 0x0800
576#define PCI_EXP_LNKSTA_SLC 0x1000
577#define PCI_EXP_LNKSTA_DLLLA 0x2000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]579#define PCI_EXP_LNKSTA_LBMS 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]580#define PCI_EXP_LNKSTA_LABS 0x8000
581#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20
582#define PCI_EXP_SLTCAP 20
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]584#define PCI_EXP_SLTCAP_ABP 0x00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]585#define PCI_EXP_SLTCAP_PCP 0x00000002
586#define PCI_EXP_SLTCAP_MRLSP 0x00000004
587#define PCI_EXP_SLTCAP_AIP 0x00000008
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]589#define PCI_EXP_SLTCAP_PIP 0x00000010
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]590#define PCI_EXP_SLTCAP_HPS 0x00000020
591#define PCI_EXP_SLTCAP_HPC 0x00000040
592#define PCI_EXP_SLTCAP_SPLV 0x00007f80
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]594#define PCI_EXP_SLTCAP_SPLS 0x00018000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]595#define PCI_EXP_SLTCAP_EIP 0x00020000
596#define PCI_EXP_SLTCAP_NCCS 0x00040000
597#define PCI_EXP_SLTCAP_PSN 0xfff80000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]599#define PCI_EXP_SLTCTL 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]600#define PCI_EXP_SLTCTL_ABPE 0x0001
601#define PCI_EXP_SLTCTL_PFDE 0x0002
602#define PCI_EXP_SLTCTL_MRLSCE 0x0004
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]604#define PCI_EXP_SLTCTL_PDCE 0x0008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]605#define PCI_EXP_SLTCTL_CCIE 0x0010
606#define PCI_EXP_SLTCTL_HPIE 0x0020
607#define PCI_EXP_SLTCTL_AIC 0x00c0
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]609#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]610#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080
611#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0
612#define PCI_EXP_SLTCTL_PIC 0x0300
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]614#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]615#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200
616#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]617#define PCI_EXP_SLTCTL_PCC 0x0400
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]619#define PCI_EXP_SLTCTL_PWR_ON 0x0000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]620#define PCI_EXP_SLTCTL_PWR_OFF 0x0400
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]621#define PCI_EXP_SLTCTL_EIC 0x0800
622#define PCI_EXP_SLTCTL_DLLSCE 0x1000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]624#define PCI_EXP_SLTSTA 26
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]625#define PCI_EXP_SLTSTA_ABP 0x0001
626#define PCI_EXP_SLTSTA_PFD 0x0002
627#define PCI_EXP_SLTSTA_MRLSC 0x0004
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]629#define PCI_EXP_SLTSTA_PDC 0x0008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]630#define PCI_EXP_SLTSTA_CC 0x0010
631#define PCI_EXP_SLTSTA_MRLSS 0x0020
632#define PCI_EXP_SLTSTA_PDS 0x0040
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]634#define PCI_EXP_SLTSTA_EIS 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]635#define PCI_EXP_SLTSTA_DLLSC 0x0100
636#define PCI_EXP_RTCTL 28
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]637#define PCI_EXP_RTCTL_SECEE 0x0001
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]639#define PCI_EXP_RTCTL_SENFEE 0x0002
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]640#define PCI_EXP_RTCTL_SEFEE 0x0004
641#define PCI_EXP_RTCTL_PMEIE 0x0008
642#define PCI_EXP_RTCTL_CRSSVE 0x0010
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]644#define PCI_EXP_RTCAP 30
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]645#define PCI_EXP_RTCAP_CRSVIS 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]646#define PCI_EXP_RTSTA 32
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]647#define PCI_EXP_RTSTA_PME 0x00010000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]649#define PCI_EXP_RTSTA_PENDING 0x00020000
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]650#define PCI_EXP_DEVCAP2 36
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]651#define PCI_EXP_DEVCAP2_ARI 0x00000020
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]652#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]654#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]655#define PCI_EXP_DEVCAP2_LTR 0x00000800
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]656#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]657#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]659#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]660#define PCI_EXP_DEVCTL2 40
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]661#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]662#define PCI_EXP_DEVCTL2_ARI 0x0020
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]664#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]665#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100
666#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]667#define PCI_EXP_DEVCTL2_LTR_EN 0x0400
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]669#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]670#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000
671#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]672#define PCI_EXP_DEVSTA2 42
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]674#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]675#define PCI_EXP_LNKCAP2 44
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]676#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]677#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]679#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]680#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]681#define PCI_EXP_LNKCTL2 48
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]682#define PCI_EXP_LNKSTA2 50
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]684#define PCI_EXP_SLTCAP2 52
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]685#define PCI_EXP_SLTCTL2 56
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]686#define PCI_EXP_SLTSTA2 58
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]687#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]689#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]690#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
691#define PCI_EXT_CAP_ID_ERR 0x01
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]692#define PCI_EXT_CAP_ID_VC 0x02
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]694#define PCI_EXT_CAP_ID_DSN 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]695#define PCI_EXT_CAP_ID_PWR 0x04
696#define PCI_EXT_CAP_ID_RCLD 0x05
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]697#define PCI_EXT_CAP_ID_RCILC 0x06
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]699#define PCI_EXT_CAP_ID_RCEC 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]700#define PCI_EXT_CAP_ID_MFVC 0x08
701#define PCI_EXT_CAP_ID_VC9 0x09
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]702#define PCI_EXT_CAP_ID_RCRB 0x0A
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]704#define PCI_EXT_CAP_ID_VNDR 0x0B
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]705#define PCI_EXT_CAP_ID_CAC 0x0C
706#define PCI_EXT_CAP_ID_ACS 0x0D
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]707#define PCI_EXT_CAP_ID_ARI 0x0E
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]709#define PCI_EXT_CAP_ID_ATS 0x0F
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]710#define PCI_EXT_CAP_ID_SRIOV 0x10
711#define PCI_EXT_CAP_ID_MRIOV 0x11
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]712#define PCI_EXT_CAP_ID_MCAST 0x12
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]714#define PCI_EXT_CAP_ID_PRI 0x13
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]715#define PCI_EXT_CAP_ID_AMD_XXX 0x14
716#define PCI_EXT_CAP_ID_REBAR 0x15
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]717#define PCI_EXT_CAP_ID_DPA 0x16
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]719#define PCI_EXT_CAP_ID_TPH 0x17
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]720#define PCI_EXT_CAP_ID_LTR 0x18
721#define PCI_EXT_CAP_ID_SECPCI 0x19
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]722#define PCI_EXT_CAP_ID_PMUX 0x1A
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]724#define PCI_EXT_CAP_ID_PASID 0x1B
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]725#define PCI_EXT_CAP_ID_DPC 0x1D
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]726#define PCI_EXT_CAP_ID_PTM 0x1F
727#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]729#define PCI_EXT_CAP_DSN_SIZEOF 12
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]730#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]731#define PCI_ERR_UNCOR_STATUS 4
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]732#define PCI_ERR_UNC_UND 0x00000001
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]734#define PCI_ERR_UNC_DLP 0x00000010
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]735#define PCI_ERR_UNC_SURPDN 0x00000020
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]736#define PCI_ERR_UNC_POISON_TLP 0x00001000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]737#define PCI_ERR_UNC_FCP 0x00002000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]739#define PCI_ERR_UNC_COMP_TIME 0x00004000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]740#define PCI_ERR_UNC_COMP_ABORT 0x00008000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]741#define PCI_ERR_UNC_UNX_COMP 0x00010000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]742#define PCI_ERR_UNC_RX_OVER 0x00020000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]744#define PCI_ERR_UNC_MALF_TLP 0x00040000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]745#define PCI_ERR_UNC_ECRC 0x00080000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]746#define PCI_ERR_UNC_UNSUP 0x00100000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]747#define PCI_ERR_UNC_ACSV 0x00200000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]749#define PCI_ERR_UNC_INTN 0x00400000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]750#define PCI_ERR_UNC_MCBTLP 0x00800000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]751#define PCI_ERR_UNC_ATOMEG 0x01000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]752#define PCI_ERR_UNC_TLPPRE 0x02000000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]754#define PCI_ERR_UNCOR_MASK 8
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]755#define PCI_ERR_UNCOR_SEVER 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]756#define PCI_ERR_COR_STATUS 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]757#define PCI_ERR_COR_RCVR 0x00000001
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]759#define PCI_ERR_COR_BAD_TLP 0x00000040
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]760#define PCI_ERR_COR_BAD_DLLP 0x00000080
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]761#define PCI_ERR_COR_REP_ROLL 0x00000100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]762#define PCI_ERR_COR_REP_TIMER 0x00001000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]764#define PCI_ERR_COR_ADV_NFAT 0x00002000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]765#define PCI_ERR_COR_INTERNAL 0x00004000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]766#define PCI_ERR_COR_LOG_OVER 0x00008000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]767#define PCI_ERR_COR_MASK 20
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]769#define PCI_ERR_CAP 24
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]770#define PCI_ERR_CAP_FEP(x) ((x) & 31)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]771#define PCI_ERR_CAP_ECRC_GENC 0x00000020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]772#define PCI_ERR_CAP_ECRC_GENE 0x00000040
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]774#define PCI_ERR_CAP_ECRC_CHKC 0x00000080
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]775#define PCI_ERR_CAP_ECRC_CHKE 0x00000100
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]776#define PCI_ERR_HEADER_LOG 28
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]777#define PCI_ERR_ROOT_COMMAND 44
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]779#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]780#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]781#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]782#define PCI_ERR_ROOT_STATUS 48
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]784#define PCI_ERR_ROOT_COR_RCV 0x00000001
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]785#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]786#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]787#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]789#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]790#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]791#define PCI_ERR_ROOT_FATAL_RCV 0x00000040
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]792#define PCI_ERR_ROOT_ERR_SRC 52
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]794#define PCI_VC_PORT_CAP1 4
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]795#define PCI_VC_CAP1_EVCC 0x00000007
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]796#define PCI_VC_CAP1_LPEVCC 0x00000070
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]797#define PCI_VC_CAP1_ARB_SIZE 0x00000c00
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]799#define PCI_VC_PORT_CAP2 8
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]800#define PCI_VC_CAP2_32_PHASE 0x00000002
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]801#define PCI_VC_CAP2_64_PHASE 0x00000004
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]802#define PCI_VC_CAP2_128_PHASE 0x00000008
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]804#define PCI_VC_CAP2_ARB_OFF 0xff000000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]805#define PCI_VC_PORT_CTRL 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]806#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]807#define PCI_VC_PORT_STATUS 14
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]809#define PCI_VC_PORT_STATUS_TABLE 0x00000001
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]810#define PCI_VC_RES_CAP 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]811#define PCI_VC_RES_CAP_32_PHASE 0x00000002
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]812#define PCI_VC_RES_CAP_64_PHASE 0x00000004
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]814#define PCI_VC_RES_CAP_128_PHASE 0x00000008
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]815#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]816#define PCI_VC_RES_CAP_256_PHASE 0x00000020
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]817#define PCI_VC_RES_CAP_ARB_OFF 0xff000000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]819#define PCI_VC_RES_CTRL 20
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]820#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]821#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]822#define PCI_VC_RES_CTRL_ID 0x07000000
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]824#define PCI_VC_RES_CTRL_ENABLE 0x80000000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]825#define PCI_VC_RES_STATUS 26
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]826#define PCI_VC_RES_STATUS_TABLE 0x00000001
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]827#define PCI_VC_RES_STATUS_NEGO 0x00000002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]829#define PCI_CAP_VC_BASE_SIZEOF 0x10
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]830#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]831#define PCI_PWR_DSR 4
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]832#define PCI_PWR_DATA 8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]834#define PCI_PWR_DATA_BASE(x) ((x) & 0xff)
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]835#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]836#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]837#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]839#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7)
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]840#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]841#define PCI_PWR_CAP 12
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]842#define PCI_PWR_CAP_BUDGET(x) ((x) & 1)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]844#define PCI_EXT_CAP_PWR_SIZEOF 16
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]845#define PCI_VNDR_HEADER 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]846#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]847#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]849#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff)
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]850#define HT_3BIT_CAP_MASK 0xE0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]851#define HT_CAPTYPE_SLAVE 0x00
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]852#define HT_CAPTYPE_HOST 0x20
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]854#define HT_5BIT_CAP_MASK 0xF8
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]855#define HT_CAPTYPE_IRQ 0x80
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]856#define HT_CAPTYPE_REMAPPING_40 0xA0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]857#define HT_CAPTYPE_REMAPPING_64 0xA2
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]859#define HT_CAPTYPE_UNITID_CLUMP 0x90
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]860#define HT_CAPTYPE_EXTCONF 0x98
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]861#define HT_CAPTYPE_MSI_MAPPING 0xA8
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]862#define HT_MSI_FLAGS 0x02
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]864#define HT_MSI_FLAGS_ENABLE 0x1
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]865#define HT_MSI_FLAGS_FIXED 0x2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]866#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]867#define HT_MSI_ADDR_LO 0x04
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]869#define HT_MSI_ADDR_LO_MASK 0xFFF00000
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]870#define HT_MSI_ADDR_HI 0x08
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]871#define HT_CAPTYPE_DIRECT_ROUTE 0xB0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]872#define HT_CAPTYPE_VCSET 0xB8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]874#define HT_CAPTYPE_ERROR_RETRY 0xC0
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]875#define HT_CAPTYPE_GEN3 0xD0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]876#define HT_CAPTYPE_PM 0xE0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]877#define HT_CAP_SIZEOF_LONG 28
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]879#define HT_CAP_SIZEOF_SHORT 24
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]880#define PCI_ARI_CAP 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]881#define PCI_ARI_CAP_MFVC 0x0001
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]882#define PCI_ARI_CAP_ACS 0x0002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]884#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff)
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]885#define PCI_ARI_CTRL 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]886#define PCI_ARI_CTRL_MFVC 0x0001
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]887#define PCI_ARI_CTRL_ACS 0x0002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]889#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7)
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]890#define PCI_EXT_CAP_ARI_SIZEOF 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]891#define PCI_ATS_CAP 0x04
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]892#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]894#define PCI_ATS_MAX_QDEP 32
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]895#define PCI_ATS_CTRL 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]896#define PCI_ATS_CTRL_ENABLE 0x8000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]897#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]899#define PCI_ATS_MIN_STU 12
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]900#define PCI_EXT_CAP_ATS_SIZEOF 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]901#define PCI_PRI_CTRL 0x04
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]902#define PCI_PRI_CTRL_ENABLE 0x01
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]904#define PCI_PRI_CTRL_RESET 0x02
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]905#define PCI_PRI_STATUS 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]906#define PCI_PRI_STATUS_RF 0x001
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]907#define PCI_PRI_STATUS_UPRGI 0x002
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]909#define PCI_PRI_STATUS_STOPPED 0x100
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]910#define PCI_PRI_MAX_REQ 0x08
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]911#define PCI_PRI_ALLOC_REQ 0x0c
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]912#define PCI_EXT_CAP_PRI_SIZEOF 16
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]914#define PCI_PASID_CAP 0x04
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]915#define PCI_PASID_CAP_EXEC 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]916#define PCI_PASID_CAP_PRIV 0x04
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]917#define PCI_PASID_CTRL 0x06
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]919#define PCI_PASID_CTRL_ENABLE 0x01
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]920#define PCI_PASID_CTRL_EXEC 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]921#define PCI_PASID_CTRL_PRIV 0x04
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]922#define PCI_EXT_CAP_PASID_SIZEOF 8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]924#define PCI_SRIOV_CAP 0x04
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]925#define PCI_SRIOV_CAP_VFM 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]926#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]927#define PCI_SRIOV_CTRL 0x08
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]929#define PCI_SRIOV_CTRL_VFE 0x01
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]930#define PCI_SRIOV_CTRL_VFM 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]931#define PCI_SRIOV_CTRL_INTR 0x04
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]932#define PCI_SRIOV_CTRL_MSE 0x08
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]934#define PCI_SRIOV_CTRL_ARI 0x10
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]935#define PCI_SRIOV_STATUS 0x0a
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]936#define PCI_SRIOV_STATUS_VFM 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]937#define PCI_SRIOV_INITIAL_VF 0x0c
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]939#define PCI_SRIOV_TOTAL_VF 0x0e
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]940#define PCI_SRIOV_NUM_VF 0x10
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]941#define PCI_SRIOV_FUNC_LINK 0x12
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]942#define PCI_SRIOV_VF_OFFSET 0x14
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]944#define PCI_SRIOV_VF_STRIDE 0x16
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]945#define PCI_SRIOV_VF_DID 0x1a
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]946#define PCI_SRIOV_SUP_PGSIZE 0x1c
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]947#define PCI_SRIOV_SYS_PGSIZE 0x20
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]949#define PCI_SRIOV_BAR 0x24
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]950#define PCI_SRIOV_NUM_BARS 6
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]951#define PCI_SRIOV_VFM 0x3c
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]952#define PCI_SRIOV_VFM_BIR(x) ((x) & 7)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]954#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]955#define PCI_SRIOV_VFM_UA 0x0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]956#define PCI_SRIOV_VFM_MI 0x1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]957#define PCI_SRIOV_VFM_MO 0x2
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]959#define PCI_SRIOV_VFM_AV 0x3
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]960#define PCI_EXT_CAP_SRIOV_SIZEOF 64
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]961#define PCI_LTR_MAX_SNOOP_LAT 0x4
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]962#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]964#define PCI_LTR_VALUE_MASK 0x000003ff
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]965#define PCI_LTR_SCALE_MASK 0x00001c00
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]966#define PCI_LTR_SCALE_SHIFT 10
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]967#define PCI_EXT_CAP_LTR_SIZEOF 8
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]969#define PCI_ACS_CAP 0x04
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]970#define PCI_ACS_SV 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]971#define PCI_ACS_TB 0x02
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]972#define PCI_ACS_RR 0x04
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]974#define PCI_ACS_CR 0x08
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]975#define PCI_ACS_UF 0x10
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]976#define PCI_ACS_EC 0x20
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]977#define PCI_ACS_DT 0x40
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]979#define PCI_ACS_EGRESS_BITS 0x05
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]980#define PCI_ACS_CTRL 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]981#define PCI_ACS_EGRESS_CTL_V 0x08
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]982#define PCI_VSEC_HDR 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]984#define PCI_VSEC_HDR_LEN_SHIFT 20
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]985#define PCI_SATA_REGS 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]986#define PCI_SATA_REGS_MASK 0xF
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]987#define PCI_SATA_REGS_INLINE 0xF
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]989#define PCI_SATA_SIZEOF_SHORT 8
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]990#define PCI_SATA_SIZEOF_LONG 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]991#define PCI_REBAR_CTRL 8
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]992#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]994#define PCI_REBAR_CTRL_NBAR_SHIFT 5
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]995#define PCI_DPA_CAP 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]996#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]997#define PCI_DPA_BASE_SIZEOF 16
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]999#define PCI_TPH_CAP 4
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]1000#define PCI_TPH_CAP_LOC_MASK 0x600
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1001#define PCI_TPH_LOC_NONE 0x000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]1002#define PCI_TPH_LOC_CAP 0x200
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1004#define PCI_TPH_LOC_MSIX 0x400
Christopher Ferris915bf812015-09-02 17:23:31 -0700[diff] [blame]1005#define PCI_TPH_CAP_ST_MASK 0x07FF0000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1006#define PCI_TPH_CAP_ST_SHIFT 16
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]1007#define PCI_TPH_BASE_SIZEOF 12
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1009#define PCI_EXP_DPC_CAP 4
1010#define PCI_EXP_DPC_CAP_RP_EXT 0x20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1011#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40
1012#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1014#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000
1015#define PCI_EXP_DPC_CTL 6
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1016#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02
1017#define PCI_EXP_DPC_CTL_INT_EN 0x08
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1018/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1019#define PCI_EXP_DPC_STATUS 8
1020#define PCI_EXP_DPC_STATUS_TRIGGER 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]1021#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08
1022#define PCI_EXP_DPC_SOURCE_ID 10
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]1024#define PCI_PTM_CAP 0x04
1025#define PCI_PTM_CAP_REQ 0x00000001
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]1026#define PCI_PTM_CAP_ROOT 0x00000004
1027#define PCI_PTM_GRANULARITY_MASK 0x0000FF00
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]1029#define PCI_PTM_CTRL 0x08
1030#define PCI_PTM_CTRL_ENABLE 0x00000001
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]1031#define PCI_PTM_CTRL_ROOT 0x00000002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1032#endif
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame]1033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */