| Elliott Hughes | 5e7f8f1 | 2022-10-01 15:10:58 +0000 | [diff] [blame^] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef _ASM_RISCV_PERF_REGS_H |
| 20 | #define _ASM_RISCV_PERF_REGS_H |
| 21 | enum perf_event_riscv_regs { |
| 22 | PERF_REG_RISCV_PC, |
| 23 | PERF_REG_RISCV_RA, |
| 24 | PERF_REG_RISCV_SP, |
| 25 | PERF_REG_RISCV_GP, |
| 26 | PERF_REG_RISCV_TP, |
| 27 | PERF_REG_RISCV_T0, |
| 28 | PERF_REG_RISCV_T1, |
| 29 | PERF_REG_RISCV_T2, |
| 30 | PERF_REG_RISCV_S0, |
| 31 | PERF_REG_RISCV_S1, |
| 32 | PERF_REG_RISCV_A0, |
| 33 | PERF_REG_RISCV_A1, |
| 34 | PERF_REG_RISCV_A2, |
| 35 | PERF_REG_RISCV_A3, |
| 36 | PERF_REG_RISCV_A4, |
| 37 | PERF_REG_RISCV_A5, |
| 38 | PERF_REG_RISCV_A6, |
| 39 | PERF_REG_RISCV_A7, |
| 40 | PERF_REG_RISCV_S2, |
| 41 | PERF_REG_RISCV_S3, |
| 42 | PERF_REG_RISCV_S4, |
| 43 | PERF_REG_RISCV_S5, |
| 44 | PERF_REG_RISCV_S6, |
| 45 | PERF_REG_RISCV_S7, |
| 46 | PERF_REG_RISCV_S8, |
| 47 | PERF_REG_RISCV_S9, |
| 48 | PERF_REG_RISCV_S10, |
| 49 | PERF_REG_RISCV_S11, |
| 50 | PERF_REG_RISCV_T3, |
| 51 | PERF_REG_RISCV_T4, |
| 52 | PERF_REG_RISCV_T5, |
| 53 | PERF_REG_RISCV_T6, |
| 54 | PERF_REG_RISCV_MAX, |
| 55 | }; |
| 56 | #endif |