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Christopher Ferris38062f92014-07-09 15:33:25 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __ARM_KVM_H__
20#define __ARM_KVM_H__
21#define KVM_SPSR_EL1 0
22#define KVM_SPSR_SVC KVM_SPSR_EL1
Christopher Ferris38062f92014-07-09 15:33:25 -070023#define KVM_SPSR_ABT 1
24#define KVM_SPSR_UND 2
25#define KVM_SPSR_IRQ 3
26#define KVM_SPSR_FIQ 4
Christopher Ferris38062f92014-07-09 15:33:25 -070027#define KVM_NR_SPSR 5
28#ifndef __ASSEMBLY__
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070029#include <linux/psci.h>
Christopher Ferris05d08e92016-02-04 13:16:38 -080030#include <linux/types.h>
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070031#include <asm/ptrace.h>
Christopher Ferris38062f92014-07-09 15:33:25 -070032#define __KVM_HAVE_GUEST_DEBUG
33#define __KVM_HAVE_IRQ_LINE
Christopher Ferris82d75042015-01-26 10:57:07 -080034#define __KVM_HAVE_READONLY_MEM
Christopher Ferris525ce912017-07-26 13:12:53 -070035#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
Tao Baod7db5942015-01-28 10:07:51 -080036#define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070037struct kvm_regs {
Tao Baod7db5942015-01-28 10:07:51 -080038 struct user_pt_regs regs;
39 __u64 sp_el1;
Tao Baod7db5942015-01-28 10:07:51 -080040 __u64 elr_el1;
41 __u64 spsr[KVM_NR_SPSR];
42 struct user_fpsimd_state fp_regs;
Christopher Ferris38062f92014-07-09 15:33:25 -070043};
Christopher Ferris82d75042015-01-26 10:57:07 -080044#define KVM_ARM_TARGET_AEM_V8 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070045#define KVM_ARM_TARGET_FOUNDATION_V8 1
Christopher Ferris38062f92014-07-09 15:33:25 -070046#define KVM_ARM_TARGET_CORTEX_A57 2
47#define KVM_ARM_TARGET_XGENE_POTENZA 3
Christopher Ferris82d75042015-01-26 10:57:07 -080048#define KVM_ARM_TARGET_CORTEX_A53 4
Christopher Ferris05d08e92016-02-04 13:16:38 -080049#define KVM_ARM_TARGET_GENERIC_V8 5
50#define KVM_ARM_NUM_TARGETS 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070051#define KVM_ARM_DEVICE_TYPE_SHIFT 0
Christopher Ferris05d08e92016-02-04 13:16:38 -080052#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
Christopher Ferris82d75042015-01-26 10:57:07 -080053#define KVM_ARM_DEVICE_ID_SHIFT 16
Christopher Ferris38062f92014-07-09 15:33:25 -070054#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
55#define KVM_ARM_DEVICE_VGIC_V2 0
Christopher Ferris05d08e92016-02-04 13:16:38 -080056#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
Christopher Ferris82d75042015-01-26 10:57:07 -080057#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
Christopher Ferris38062f92014-07-09 15:33:25 -070058#define KVM_VGIC_V2_DIST_SIZE 0x1000
59#define KVM_VGIC_V2_CPU_SIZE 0x2000
Christopher Ferris05d08e92016-02-04 13:16:38 -080060#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
61#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
Christopher Ferris49f525c2016-12-12 14:55:36 -080062#define KVM_VGIC_ITS_ADDR_TYPE 4
Christopher Ferris05d08e92016-02-04 13:16:38 -080063#define KVM_VGIC_V3_DIST_SIZE SZ_64K
Christopher Ferris49f525c2016-12-12 14:55:36 -080064#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
65#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
Christopher Ferris05d08e92016-02-04 13:16:38 -080066#define KVM_ARM_VCPU_POWER_OFF 0
Christopher Ferris82d75042015-01-26 10:57:07 -080067#define KVM_ARM_VCPU_EL1_32BIT 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070068#define KVM_ARM_VCPU_PSCI_0_2 2
Christopher Ferris106b3a82016-08-24 12:15:38 -070069#define KVM_ARM_VCPU_PMU_V3 3
Christopher Ferris106b3a82016-08-24 12:15:38 -070070struct kvm_vcpu_init {
Christopher Ferris05d08e92016-02-04 13:16:38 -080071 __u32 target;
Tao Baod7db5942015-01-28 10:07:51 -080072 __u32 features[7];
Christopher Ferris38062f92014-07-09 15:33:25 -070073};
Christopher Ferris106b3a82016-08-24 12:15:38 -070074struct kvm_sregs {
Christopher Ferris05d08e92016-02-04 13:16:38 -080075};
Christopher Ferris82d75042015-01-26 10:57:07 -080076struct kvm_fpu {
Christopher Ferris38062f92014-07-09 15:33:25 -070077};
Christopher Ferris106b3a82016-08-24 12:15:38 -070078#define KVM_ARM_MAX_DBG_REGS 16
Christopher Ferris05d08e92016-02-04 13:16:38 -080079struct kvm_guest_debug_arch {
80 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
81 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
Christopher Ferris106b3a82016-08-24 12:15:38 -070082 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
Christopher Ferris05d08e92016-02-04 13:16:38 -080083 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
Christopher Ferris38062f92014-07-09 15:33:25 -070084};
Christopher Ferris05d08e92016-02-04 13:16:38 -080085struct kvm_debug_exit_arch {
Christopher Ferris106b3a82016-08-24 12:15:38 -070086 __u32 hsr;
Christopher Ferris05d08e92016-02-04 13:16:38 -080087 __u64 far;
88};
89#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
Christopher Ferris106b3a82016-08-24 12:15:38 -070090#define KVM_GUESTDBG_USE_HW (1 << 17)
Christopher Ferris38062f92014-07-09 15:33:25 -070091struct kvm_sync_regs {
Christopher Ferris525ce912017-07-26 13:12:53 -070092 __u64 device_irq_level;
Christopher Ferris38062f92014-07-09 15:33:25 -070093};
Christopher Ferris82d75042015-01-26 10:57:07 -080094struct kvm_arch_memory_slot {
Christopher Ferris106b3a82016-08-24 12:15:38 -070095};
Christopher Ferris38062f92014-07-09 15:33:25 -070096#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
97#define KVM_REG_ARM_COPROC_SHIFT 16
Christopher Ferris82d75042015-01-26 10:57:07 -080098#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
Christopher Ferris106b3a82016-08-24 12:15:38 -070099#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
Christopher Ferris38062f92014-07-09 15:33:25 -0700100#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
101#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
Christopher Ferris82d75042015-01-26 10:57:07 -0800102#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700103#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700104#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
105#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
Christopher Ferris82d75042015-01-26 10:57:07 -0800106#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700107#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
Christopher Ferris38062f92014-07-09 15:33:25 -0700108#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
109#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
Christopher Ferris82d75042015-01-26 10:57:07 -0800110#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
Christopher Ferris106b3a82016-08-24 12:15:38 -0700111#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
Christopher Ferris38062f92014-07-09 15:33:25 -0700112#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
113#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
Christopher Ferris82d75042015-01-26 10:57:07 -0800114#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700115#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
Christopher Ferris38062f92014-07-09 15:33:25 -0700116#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
Tao Baod7db5942015-01-28 10:07:51 -0800117#define ARM64_SYS_REG_SHIFT_MASK(x,n) (((x) << KVM_REG_ARM64_SYSREG_ ##n ##_SHIFT) & KVM_REG_ARM64_SYSREG_ ##n ##_MASK)
Tao Baod7db5942015-01-28 10:07:51 -0800118#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
Christopher Ferris106b3a82016-08-24 12:15:38 -0700119#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
Christopher Ferris38062f92014-07-09 15:33:25 -0700120#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
121#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
Christopher Ferris82d75042015-01-26 10:57:07 -0800122#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700123#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
Christopher Ferris38062f92014-07-09 15:33:25 -0700124#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
125#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
Christopher Ferris82d75042015-01-26 10:57:07 -0800126#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
Christopher Ferris525ce912017-07-26 13:12:53 -0700128#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
129#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700130#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
131#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
Christopher Ferris525ce912017-07-26 13:12:53 -0700132#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
Christopher Ferris82d75042015-01-26 10:57:07 -0800133#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700134#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
Christopher Ferris525ce912017-07-26 13:12:53 -0700135#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
136#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
137#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
138#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
139#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
140#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
141#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
142#define VGIC_LEVEL_INFO_LINE_LEVEL 0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800143#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
Christopher Ferris525ce912017-07-26 13:12:53 -0700144#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
145#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
146#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700147#define KVM_ARM_VCPU_PMU_V3_CTRL 0
148#define KVM_ARM_VCPU_PMU_V3_IRQ 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700149#define KVM_ARM_VCPU_PMU_V3_INIT 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800150#define KVM_ARM_IRQ_TYPE_SHIFT 24
Christopher Ferris38062f92014-07-09 15:33:25 -0700151#define KVM_ARM_IRQ_TYPE_MASK 0xff
152#define KVM_ARM_IRQ_VCPU_SHIFT 16
153#define KVM_ARM_IRQ_VCPU_MASK 0xff
Christopher Ferris38062f92014-07-09 15:33:25 -0700154#define KVM_ARM_IRQ_NUM_SHIFT 0
155#define KVM_ARM_IRQ_NUM_MASK 0xffff
156#define KVM_ARM_IRQ_TYPE_CPU 0
157#define KVM_ARM_IRQ_TYPE_SPI 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700158#define KVM_ARM_IRQ_TYPE_PPI 2
159#define KVM_ARM_IRQ_CPU_IRQ 0
160#define KVM_ARM_IRQ_CPU_FIQ 1
161#define KVM_ARM_IRQ_GIC_MAX 127
Christopher Ferris05d08e92016-02-04 13:16:38 -0800162#define KVM_NR_IRQCHIPS 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700163#define KVM_PSCI_FN_BASE 0x95c1ba5e
164#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800165#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
Christopher Ferris38062f92014-07-09 15:33:25 -0700166#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
Christopher Ferris38062f92014-07-09 15:33:25 -0700167#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
168#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800169#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700170#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
171#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700172#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
Christopher Ferris49f525c2016-12-12 14:55:36 -0800173#endif
174#endif