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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
24#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
Christopher Ferris38062f92014-07-09 15:33:25 -070025#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -070026struct drm_tegra_gem_create {
Tao Baod7db5942015-01-28 10:07:51 -080027 __u64 size;
28 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -080029 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -070030};
Ben Cheng655a7c02013-10-16 16:09:24 -070031struct drm_tegra_gem_mmap {
Tao Baod7db5942015-01-28 10:07:51 -080032 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -080033 __u32 pad;
34 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070035};
Ben Cheng655a7c02013-10-16 16:09:24 -070036struct drm_tegra_syncpt_read {
Christopher Ferris05d08e92016-02-04 13:16:38 -080037 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -080038 __u32 value;
Ben Cheng655a7c02013-10-16 16:09:24 -070039};
Ben Cheng655a7c02013-10-16 16:09:24 -070040struct drm_tegra_syncpt_incr {
Christopher Ferris05d08e92016-02-04 13:16:38 -080041 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -080042 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -070043};
Ben Cheng655a7c02013-10-16 16:09:24 -070044struct drm_tegra_syncpt_wait {
Christopher Ferris05d08e92016-02-04 13:16:38 -080045 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -080046 __u32 thresh;
47 __u32 timeout;
48 __u32 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -080049};
Ben Cheng655a7c02013-10-16 16:09:24 -070050#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
51struct drm_tegra_open_channel {
Tao Baod7db5942015-01-28 10:07:51 -080052 __u32 client;
Christopher Ferris05d08e92016-02-04 13:16:38 -080053 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -080054 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -070055};
Ben Cheng655a7c02013-10-16 16:09:24 -070056struct drm_tegra_close_channel {
Christopher Ferris05d08e92016-02-04 13:16:38 -080057 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -070058};
59struct drm_tegra_get_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -080060 __u64 context;
Christopher Ferris05d08e92016-02-04 13:16:38 -080061 __u32 index;
Tao Baod7db5942015-01-28 10:07:51 -080062 __u32 id;
Christopher Ferris38062f92014-07-09 15:33:25 -070063};
64struct drm_tegra_get_syncpt_base {
Christopher Ferris05d08e92016-02-04 13:16:38 -080065 __u64 context;
Tao Baod7db5942015-01-28 10:07:51 -080066 __u32 syncpt;
67 __u32 id;
Ben Cheng655a7c02013-10-16 16:09:24 -070068};
Christopher Ferris05d08e92016-02-04 13:16:38 -080069struct drm_tegra_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -080070 __u32 id;
71 __u32 incrs;
Ben Cheng655a7c02013-10-16 16:09:24 -070072};
Christopher Ferris05d08e92016-02-04 13:16:38 -080073struct drm_tegra_cmdbuf {
Tao Baod7db5942015-01-28 10:07:51 -080074 __u32 handle;
75 __u32 offset;
76 __u32 words;
Christopher Ferris05d08e92016-02-04 13:16:38 -080077 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -070078};
79struct drm_tegra_reloc {
Tao Baod7db5942015-01-28 10:07:51 -080080 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -080081 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -080082 __u32 offset;
83 } cmdbuf;
84 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -080085 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -080086 __u32 offset;
87 } target;
88 __u32 shift;
Christopher Ferris05d08e92016-02-04 13:16:38 -080089 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -070090};
91struct drm_tegra_waitchk {
Tao Baod7db5942015-01-28 10:07:51 -080092 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -080093 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -080094 __u32 syncpt;
95 __u32 thresh;
Ben Cheng655a7c02013-10-16 16:09:24 -070096};
Christopher Ferris05d08e92016-02-04 13:16:38 -080097struct drm_tegra_submit {
Tao Baod7db5942015-01-28 10:07:51 -080098 __u64 context;
99 __u32 num_syncpts;
100 __u32 num_cmdbufs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800101 __u32 num_relocs;
Tao Baod7db5942015-01-28 10:07:51 -0800102 __u32 num_waitchks;
103 __u32 waitchk_mask;
104 __u32 timeout;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800105 __u64 syncpts;
Tao Baod7db5942015-01-28 10:07:51 -0800106 __u64 cmdbufs;
107 __u64 relocs;
108 __u64 waitchks;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109 __u32 fence;
Tao Baod7db5942015-01-28 10:07:51 -0800110 __u32 reserved[5];
Ben Cheng655a7c02013-10-16 16:09:24 -0700111};
Christopher Ferris82d75042015-01-26 10:57:07 -0800112#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800114#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
115struct drm_tegra_gem_set_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800116 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800117 __u32 mode;
Tao Baod7db5942015-01-28 10:07:51 -0800118 __u32 value;
119 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800120};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800121struct drm_tegra_gem_get_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800122 __u32 handle;
123 __u32 mode;
124 __u32 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800125 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800126};
127#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
128#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
129struct drm_tegra_gem_set_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800130 __u32 handle;
131 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800132};
133struct drm_tegra_gem_get_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800134 __u32 handle;
135 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800136};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800137#define DRM_TEGRA_GEM_CREATE 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800138#define DRM_TEGRA_GEM_MMAP 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700139#define DRM_TEGRA_SYNCPT_READ 0x02
140#define DRM_TEGRA_SYNCPT_INCR 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141#define DRM_TEGRA_SYNCPT_WAIT 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800142#define DRM_TEGRA_OPEN_CHANNEL 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700143#define DRM_TEGRA_CLOSE_CHANNEL 0x06
144#define DRM_TEGRA_GET_SYNCPT 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800145#define DRM_TEGRA_SUBMIT 0x08
Christopher Ferris82d75042015-01-26 10:57:07 -0800146#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
147#define DRM_TEGRA_GEM_SET_TILING 0x0a
148#define DRM_TEGRA_GEM_GET_TILING 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800149#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
Christopher Ferris82d75042015-01-26 10:57:07 -0800150#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -0700151#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
152#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800153#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
Christopher Ferris82d75042015-01-26 10:57:07 -0800154#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
Ben Cheng655a7c02013-10-16 16:09:24 -0700155#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
156#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferris9ce28842018-10-25 12:11:39 -0700157#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
Christopher Ferris82d75042015-01-26 10:57:07 -0800158#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
Ben Cheng655a7c02013-10-16 16:09:24 -0700159#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
Christopher Ferris38062f92014-07-09 15:33:25 -0700160#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800161#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
Christopher Ferris82d75042015-01-26 10:57:07 -0800162#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
163#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
164#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700165#ifdef __cplusplus
166#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800167#endif