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Christopher Ferris05d08e92016-02-04 13:16:38 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef VIRTGPU_DRM_H
20#define VIRTGPU_DRM_H
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris05d08e92016-02-04 13:16:38 -080023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -080025#define DRM_VIRTGPU_MAP 0x01
26#define DRM_VIRTGPU_EXECBUFFER 0x02
27#define DRM_VIRTGPU_GETPARAM 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -080028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070029#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
Christopher Ferris05d08e92016-02-04 13:16:38 -080030#define DRM_VIRTGPU_RESOURCE_INFO 0x05
31#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
32#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -080033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070034#define DRM_VIRTGPU_WAIT 0x08
Christopher Ferris05d08e92016-02-04 13:16:38 -080035#define DRM_VIRTGPU_GET_CAPS 0x09
36struct drm_virtgpu_map {
Christopher Ferris106b3a82016-08-24 12:15:38 -070037 __u64 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070039 __u32 handle;
40 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -080041};
42struct drm_virtgpu_execbuffer {
Christopher Ferris05d08e92016-02-04 13:16:38 -080043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070044 __u32 flags;
45 __u32 size;
46 __u64 command;
47 __u64 bo_handles;
Christopher Ferris05d08e92016-02-04 13:16:38 -080048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070049 __u32 num_bo_handles;
50 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -080051};
52#define VIRTGPU_PARAM_3D_FEATURES 1
Christopher Ferris106b3a82016-08-24 12:15:38 -070053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080054struct drm_virtgpu_getparam {
Christopher Ferris106b3a82016-08-24 12:15:38 -070055 __u64 param;
56 __u64 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -080057};
Christopher Ferris106b3a82016-08-24 12:15:38 -070058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080059struct drm_virtgpu_resource_create {
Christopher Ferris106b3a82016-08-24 12:15:38 -070060 __u32 target;
61 __u32 format;
62 __u32 bind;
Christopher Ferris05d08e92016-02-04 13:16:38 -080063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070064 __u32 width;
65 __u32 height;
66 __u32 depth;
67 __u32 array_size;
Christopher Ferris05d08e92016-02-04 13:16:38 -080068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070069 __u32 last_level;
70 __u32 nr_samples;
71 __u32 flags;
72 __u32 bo_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -080073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070074 __u32 res_handle;
75 __u32 size;
76 __u32 stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -080077};
Christopher Ferris106b3a82016-08-24 12:15:38 -070078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080079struct drm_virtgpu_resource_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -070080 __u32 bo_handle;
81 __u32 res_handle;
82 __u32 size;
Christopher Ferris05d08e92016-02-04 13:16:38 -080083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070084 __u32 stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -080085};
86struct drm_virtgpu_3d_box {
Christopher Ferris106b3a82016-08-24 12:15:38 -070087 __u32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -080088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070089 __u32 y;
90 __u32 z;
91 __u32 w;
92 __u32 h;
Christopher Ferris05d08e92016-02-04 13:16:38 -080093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070094 __u32 d;
Christopher Ferris05d08e92016-02-04 13:16:38 -080095};
96struct drm_virtgpu_3d_transfer_to_host {
Christopher Ferris106b3a82016-08-24 12:15:38 -070097 __u32 bo_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -080098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -070099 struct drm_virtgpu_3d_box box;
100 __u32 level;
101 __u32 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800102};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800104struct drm_virtgpu_3d_transfer_from_host {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700105 __u32 bo_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106 struct drm_virtgpu_3d_box box;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700107 __u32 level;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700109 __u32 offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110};
111#define VIRTGPU_WAIT_NOWAIT 1
112struct drm_virtgpu_3d_wait {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700114 __u32 handle;
115 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800116};
117struct drm_virtgpu_get_caps {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700119 __u32 cap_set_id;
120 __u32 cap_set_ver;
121 __u64 addr;
122 __u32 size;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700124 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800125};
126#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
127#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700129#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800130#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
131#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
132#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700134#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800135#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
136#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700137#ifdef __cplusplus
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800140#endif