blob: 9f6cdb7b66ea631c4f6ecdb7e0bc4f504d26ee8b [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_HDLCDRV_H
20#define _UAPI_HDLCDRV_H
21struct hdlcdrv_params {
Tao Baod7db5942015-01-28 10:07:51 -080022 int iobase;
Tao Baod7db5942015-01-28 10:07:51 -080023 int irq;
24 int dma;
25 int dma2;
26 int seriobase;
Tao Baod7db5942015-01-28 10:07:51 -080027 int pariobase;
28 int midiiobase;
Ben Cheng655a7c02013-10-16 16:09:24 -070029};
30struct hdlcdrv_channel_params {
Tao Baod7db5942015-01-28 10:07:51 -080031 int tx_delay;
32 int tx_tail;
33 int slottime;
34 int ppersist;
Tao Baod7db5942015-01-28 10:07:51 -080035 int fulldup;
Ben Cheng655a7c02013-10-16 16:09:24 -070036};
37struct hdlcdrv_old_channel_state {
Tao Baod7db5942015-01-28 10:07:51 -080038 int ptt;
Tao Baod7db5942015-01-28 10:07:51 -080039 int dcd;
40 int ptt_keyed;
Ben Cheng655a7c02013-10-16 16:09:24 -070041};
42struct hdlcdrv_channel_state {
Tao Baod7db5942015-01-28 10:07:51 -080043 int ptt;
44 int dcd;
45 int ptt_keyed;
46 unsigned long tx_packets;
Tao Baod7db5942015-01-28 10:07:51 -080047 unsigned long tx_errors;
48 unsigned long rx_packets;
49 unsigned long rx_errors;
Ben Cheng655a7c02013-10-16 16:09:24 -070050};
Ben Cheng655a7c02013-10-16 16:09:24 -070051struct hdlcdrv_ioctl {
Tao Baod7db5942015-01-28 10:07:51 -080052 int cmd;
53 union {
54 struct hdlcdrv_params mp;
Tao Baod7db5942015-01-28 10:07:51 -080055 struct hdlcdrv_channel_params cp;
56 struct hdlcdrv_channel_state cs;
57 struct hdlcdrv_old_channel_state ocs;
58 unsigned int calibrate;
Tao Baod7db5942015-01-28 10:07:51 -080059 unsigned char bits;
60 char modename[128];
61 char drivername[32];
62 } data;
Ben Cheng655a7c02013-10-16 16:09:24 -070063};
64#define HDLCDRVCTL_GETMODEMPAR 0
65#define HDLCDRVCTL_SETMODEMPAR 1
66#define HDLCDRVCTL_MODEMPARMASK 2
Ben Cheng655a7c02013-10-16 16:09:24 -070067#define HDLCDRVCTL_GETCHANNELPAR 10
68#define HDLCDRVCTL_SETCHANNELPAR 11
69#define HDLCDRVCTL_OLDGETSTAT 20
70#define HDLCDRVCTL_CALIBRATE 21
Ben Cheng655a7c02013-10-16 16:09:24 -070071#define HDLCDRVCTL_GETSTAT 22
72#define HDLCDRVCTL_GETSAMPLES 30
73#define HDLCDRVCTL_GETBITS 31
74#define HDLCDRVCTL_GETMODE 40
Ben Cheng655a7c02013-10-16 16:09:24 -070075#define HDLCDRVCTL_SETMODE 41
76#define HDLCDRVCTL_MODELIST 42
77#define HDLCDRVCTL_DRIVERNAME 43
Tao Baod7db5942015-01-28 10:07:51 -080078#define HDLCDRV_PARMASK_IOBASE (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -080079#define HDLCDRV_PARMASK_IRQ (1 << 1)
80#define HDLCDRV_PARMASK_DMA (1 << 2)
81#define HDLCDRV_PARMASK_DMA2 (1 << 3)
82#define HDLCDRV_PARMASK_SERIOBASE (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -080083#define HDLCDRV_PARMASK_PARIOBASE (1 << 5)
84#define HDLCDRV_PARMASK_MIDIIOBASE (1 << 6)
Ben Cheng655a7c02013-10-16 16:09:24 -070085#endif