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gerrit.omnirom.org / android_bionic / 24f97eb27bc131801ed9d0d2b367d4164424ac77 / . / libc / kernel / uapi / misc / habanalabs.h
blob: c2e25de6d7229134c2ed698006efbab7037d9e98 [file] [log] [blame]
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700[diff] [blame^]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef HABANALABS_H_
20#define HABANALABS_H_
21#include <linux/types.h>
22#include <linux/ioctl.h>
23#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000
24enum goya_queue_id {
25 GOYA_QUEUE_ID_DMA_0 = 0,
26 GOYA_QUEUE_ID_DMA_1,
27 GOYA_QUEUE_ID_DMA_2,
28 GOYA_QUEUE_ID_DMA_3,
29 GOYA_QUEUE_ID_DMA_4,
30 GOYA_QUEUE_ID_CPU_PQ,
31 GOYA_QUEUE_ID_MME,
32 GOYA_QUEUE_ID_TPC0,
33 GOYA_QUEUE_ID_TPC1,
34 GOYA_QUEUE_ID_TPC2,
35 GOYA_QUEUE_ID_TPC3,
36 GOYA_QUEUE_ID_TPC4,
37 GOYA_QUEUE_ID_TPC5,
38 GOYA_QUEUE_ID_TPC6,
39 GOYA_QUEUE_ID_TPC7,
40 GOYA_QUEUE_ID_SIZE
41};
42#define HL_INFO_HW_IP_INFO 0
43#define HL_INFO_HW_EVENTS 1
44#define HL_INFO_DRAM_USAGE 2
45#define HL_INFO_HW_IDLE 3
46#define HL_INFO_VERSION_MAX_LEN 128
47struct hl_info_hw_ip_info {
48 __u64 sram_base_address;
49 __u64 dram_base_address;
50 __u64 dram_size;
51 __u32 sram_size;
52 __u32 num_of_events;
53 __u32 device_id;
54 __u32 reserved[3];
55 __u32 armcp_cpld_version;
56 __u32 psoc_pci_pll_nr;
57 __u32 psoc_pci_pll_nf;
58 __u32 psoc_pci_pll_od;
59 __u32 psoc_pci_pll_div_factor;
60 __u8 tpc_enabled_mask;
61 __u8 dram_enabled;
62 __u8 pad[2];
63 __u8 armcp_version[HL_INFO_VERSION_MAX_LEN];
64};
65struct hl_info_dram_usage {
66 __u64 dram_free_mem;
67 __u64 ctx_dram_mem;
68};
69struct hl_info_hw_idle {
70 __u32 is_idle;
71 __u32 pad;
72};
73struct hl_info_args {
74 __u64 return_pointer;
75 __u32 return_size;
76 __u32 op;
77 __u32 ctx_id;
78 __u32 pad;
79};
80#define HL_CB_OP_CREATE 0
81#define HL_CB_OP_DESTROY 1
82struct hl_cb_in {
83 __u64 cb_handle;
84 __u32 op;
85 __u32 cb_size;
86 __u32 ctx_id;
87 __u32 pad;
88};
89struct hl_cb_out {
90 __u64 cb_handle;
91};
92union hl_cb_args {
93 struct hl_cb_in in;
94 struct hl_cb_out out;
95};
96struct hl_cs_chunk {
97 __u64 cb_handle;
98 __u32 queue_index;
99 __u32 cb_size;
100 __u32 cs_chunk_flags;
101 __u32 pad[11];
102};
103#define HL_CS_FLAGS_FORCE_RESTORE 0x1
104#define HL_CS_STATUS_SUCCESS 0
105struct hl_cs_in {
106 __u64 chunks_restore;
107 __u64 chunks_execute;
108 __u64 chunks_store;
109 __u32 num_chunks_restore;
110 __u32 num_chunks_execute;
111 __u32 num_chunks_store;
112 __u32 cs_flags;
113 __u32 ctx_id;
114};
115struct hl_cs_out {
116 __u64 seq;
117 __u32 status;
118 __u32 pad;
119};
120union hl_cs_args {
121 struct hl_cs_in in;
122 struct hl_cs_out out;
123};
124struct hl_wait_cs_in {
125 __u64 seq;
126 __u64 timeout_us;
127 __u32 ctx_id;
128 __u32 pad;
129};
130#define HL_WAIT_CS_STATUS_COMPLETED 0
131#define HL_WAIT_CS_STATUS_BUSY 1
132#define HL_WAIT_CS_STATUS_TIMEDOUT 2
133#define HL_WAIT_CS_STATUS_ABORTED 3
134#define HL_WAIT_CS_STATUS_INTERRUPTED 4
135struct hl_wait_cs_out {
136 __u32 status;
137 __u32 pad;
138};
139union hl_wait_cs_args {
140 struct hl_wait_cs_in in;
141 struct hl_wait_cs_out out;
142};
143#define HL_MEM_OP_ALLOC 0
144#define HL_MEM_OP_FREE 1
145#define HL_MEM_OP_MAP 2
146#define HL_MEM_OP_UNMAP 3
147#define HL_MEM_CONTIGUOUS 0x1
148#define HL_MEM_SHARED 0x2
149#define HL_MEM_USERPTR 0x4
150struct hl_mem_in {
151 union {
152 struct {
153 __u64 mem_size;
154 } alloc;
155 struct {
156 __u64 handle;
157 } free;
158 struct {
159 __u64 hint_addr;
160 __u64 handle;
161 } map_device;
162 struct {
163 __u64 host_virt_addr;
164 __u64 hint_addr;
165 __u64 mem_size;
166 } map_host;
167 struct {
168 __u64 device_virt_addr;
169 } unmap;
170 };
171 __u32 op;
172 __u32 flags;
173 __u32 ctx_id;
174 __u32 pad;
175};
176struct hl_mem_out {
177 union {
178 __u64 device_virt_addr;
179 __u64 handle;
180 };
181};
182union hl_mem_args {
183 struct hl_mem_in in;
184 struct hl_mem_out out;
185};
186#define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args)
187#define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args)
188#define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args)
189#define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args)
190#define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args)
191#define HL_COMMAND_START 0x01
192#define HL_COMMAND_END 0x06
193#endif