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gerrit.omnirom.org / android_bionic / 180edefbd287c39caeb9d48784a9a10ac35f3636 / . / libc / kernel / uapi / video / sisfb.h
blob: cbe525a014a89ee06d66b358102af3fee4cb5147 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame^]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]7#ifndef _UAPI_LINUX_SISFB_H_
8#define _UAPI_LINUX_SISFB_H_
9#include <linux/types.h>
10#include <asm/ioctl.h>
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]11#define CRT2_DEFAULT 0x00000001
12#define CRT2_LCD 0x00000002
13#define CRT2_TV 0x00000004
14#define CRT2_VGA 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]15#define TV_NTSC 0x00000010
16#define TV_PAL 0x00000020
17#define TV_HIVISION 0x00000040
18#define TV_YPBPR 0x00000080
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]19#define TV_AVIDEO 0x00000100
20#define TV_SVIDEO 0x00000200
21#define TV_SCART 0x00000400
22#define TV_PALM 0x00001000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23#define TV_PALN 0x00002000
24#define TV_NTSCJ 0x00001000
25#define TV_CHSCART 0x00008000
26#define TV_CHYPBPR525I 0x00010000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27#define CRT1_VGA 0x00000000
28#define CRT1_LCDA 0x00020000
29#define VGA2_CONNECTED 0x00040000
30#define VB_DISPTYPE_CRT1 0x00080000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31#define VB_SINGLE_MODE 0x20000000
32#define VB_MIRROR_MODE 0x40000000
33#define VB_DUALVIEW_MODE 0x80000000
34#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35#define TV_STANDARD (TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]36#define TV_INTERFACE (TV_AVIDEO | TV_SVIDEO | TV_SCART | TV_HIVISION | TV_YPBPR | TV_CHSCART | TV_CHYPBPR525I)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]37#define TV_YPBPR525I TV_NTSC
38#define TV_YPBPR525P TV_PAL
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define TV_YPBPR750P TV_PALM
40#define TV_YPBPR1080I TV_PALN
41#define TV_YPBPRALL (TV_YPBPR525I | TV_YPBPR525P | TV_YPBPR750P | TV_YPBPR1080I)
42#define VB_DISPTYPE_DISP2 CRT2_ENABLE
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43#define VB_DISPTYPE_CRT2 CRT2_ENABLE
44#define VB_DISPTYPE_DISP1 VB_DISPTYPE_CRT1
45#define VB_DISPMODE_SINGLE VB_SINGLE_MODE
46#define VB_DISPMODE_MIRROR VB_MIRROR_MODE
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47#define VB_DISPMODE_DUAL VB_DUALVIEW_MODE
48#define VB_DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE)
49struct sisfb_info {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]50 __u32 sisfb_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51#ifndef SISFB_ID
52#define SISFB_ID 0x53495346
53#endif
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54 __u32 chip_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]55 __u32 memory;
56 __u32 heapstart;
57 __u8 fbvidmode;
58 __u8 sisfb_version;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59 __u8 sisfb_revision;
60 __u8 sisfb_patchlevel;
61 __u8 sisfb_caps;
62 __u32 sisfb_tqlen;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]63 __u32 sisfb_pcibus;
64 __u32 sisfb_pcislot;
65 __u32 sisfb_pcifunc;
66 __u8 sisfb_lcdpdc;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]67 __u8 sisfb_lcda;
68 __u32 sisfb_vbflags;
69 __u32 sisfb_currentvbflags;
70 __u32 sisfb_scalelcd;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]71 __u32 sisfb_specialtiming;
72 __u8 sisfb_haveemi;
73 __u8 sisfb_emi30, sisfb_emi31, sisfb_emi32, sisfb_emi33;
74 __u8 sisfb_haveemilcd;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]75 __u8 sisfb_lcdpdca;
76 __u16 sisfb_tvxpos, sisfb_tvypos;
77 __u32 sisfb_heapsize;
78 __u32 sisfb_videooffset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 __u32 sisfb_curfstn;
80 __u32 sisfb_curdstn;
81 __u16 sisfb_pci_vendor;
82 __u32 sisfb_vbflags2;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]83 __u8 sisfb_can_post;
84 __u8 sisfb_card_posted;
85 __u8 sisfb_was_boot_device;
86 __u8 reserved[183];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87};
88#define SISFB_CMD_GETVBFLAGS 0x55AA0001
89#define SISFB_CMD_SWITCHCRT1 0x55AA0010
90#define SISFB_CMD_ERR_OK 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]91#define SISFB_CMD_ERR_LOCKED 0x80000001
92#define SISFB_CMD_ERR_EARLY 0x80000002
93#define SISFB_CMD_ERR_NOVB 0x80000003
94#define SISFB_CMD_ERR_NOCRT2 0x80000004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95#define SISFB_CMD_ERR_UNKNOWN 0x8000ffff
96#define SISFB_CMD_ERR_OTHER 0x80010000
97struct sisfb_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]98 __u32 sisfb_cmd;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]99 __u32 sisfb_arg[16];
100 __u32 sisfb_result[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]101};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]102#define SISFB_GET_INFO_SIZE _IOR(0xF3, 0x00, __u32)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]103#define SISFB_GET_INFO _IOR(0xF3, 0x01, struct sisfb_info)
104#define SISFB_GET_VBRSTATUS _IOR(0xF3, 0x02, __u32)
105#define SISFB_GET_AUTOMAXIMIZE _IOR(0xF3, 0x03, __u32)
106#define SISFB_SET_AUTOMAXIMIZE _IOW(0xF3, 0x03, __u32)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]107#define SISFB_GET_TVPOSOFFSET _IOR(0xF3, 0x04, __u32)
108#define SISFB_SET_TVPOSOFFSET _IOW(0xF3, 0x04, __u32)
109#define SISFB_COMMAND _IOWR(0xF3, 0x05, struct sisfb_cmd)
110#define SISFB_SET_LOCK _IOW(0xF3, 0x06, __u32)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]111#define SISFB_GET_INFO_OLD _IOR('n', 0xF8, __u32)
112#define SISFB_GET_VBRSTATUS_OLD _IOR('n', 0xF9, __u32)
113#define SISFB_GET_AUTOMAXIMIZE_OLD _IOR('n', 0xFA, __u32)
114#define SISFB_SET_AUTOMAXIMIZE_OLD _IOW('n', 0xFA, __u32)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115struct sis_memreq {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]116 __u32 offset;
117 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]118};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119#endif