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gerrit.omnirom.org / android_bionic / 180edefbd287c39caeb9d48784a9a10ac35f3636 / . / libc / kernel / uapi / linux / can / netlink.h
blob: c9b455b30bef593b8b5a34d4f425c38d3baf1334 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame^]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]7#ifndef _UAPI_CAN_NETLINK_H
8#define _UAPI_CAN_NETLINK_H
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]9#include <linux/types.h>
10struct can_bittiming {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]11 __u32 bitrate;
12 __u32 sample_point;
13 __u32 tq;
14 __u32 prop_seg;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]15 __u32 phase_seg1;
16 __u32 phase_seg2;
17 __u32 sjw;
18 __u32 brp;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]19};
20struct can_bittiming_const {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]21 char name[16];
22 __u32 tseg1_min;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]23 __u32 tseg1_max;
24 __u32 tseg2_min;
25 __u32 tseg2_max;
26 __u32 sjw_max;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]27 __u32 brp_min;
28 __u32 brp_max;
29 __u32 brp_inc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31struct can_clock {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]32 __u32 freq;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33};
34enum can_state {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]35 CAN_STATE_ERROR_ACTIVE = 0,
36 CAN_STATE_ERROR_WARNING,
37 CAN_STATE_ERROR_PASSIVE,
38 CAN_STATE_BUS_OFF,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39 CAN_STATE_STOPPED,
40 CAN_STATE_SLEEPING,
41 CAN_STATE_MAX
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]42};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43struct can_berr_counter {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44 __u16 txerr;
45 __u16 rxerr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47struct can_ctrlmode {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]48 __u32 mask;
49 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51#define CAN_CTRLMODE_LOOPBACK 0x01
52#define CAN_CTRLMODE_LISTENONLY 0x02
53#define CAN_CTRLMODE_3_SAMPLES 0x04
54#define CAN_CTRLMODE_ONE_SHOT 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]55#define CAN_CTRLMODE_BERR_REPORTING 0x10
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]56#define CAN_CTRLMODE_FD 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]57#define CAN_CTRLMODE_PRESUME_ACK 0x40
Christopher Ferrise01d32f2015-03-31 14:57:48 -0700[diff] [blame]58#define CAN_CTRLMODE_FD_NON_ISO 0x80
Christopher Ferris05667cd2021-02-16 16:01:34 -0800[diff] [blame]59#define CAN_CTRLMODE_CC_LEN8_DLC 0x100
Christopher Ferrisa4792612022-01-10 13:51:15 -0800[diff] [blame]60#define CAN_CTRLMODE_TDC_AUTO 0x200
61#define CAN_CTRLMODE_TDC_MANUAL 0x400
Christopher Ferrise01d32f2015-03-31 14:57:48 -0700[diff] [blame]62struct can_device_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]63 __u32 bus_error;
64 __u32 error_warning;
65 __u32 error_passive;
Christopher Ferrise01d32f2015-03-31 14:57:48 -0700[diff] [blame]66 __u32 bus_off;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]67 __u32 arbitration_lost;
68 __u32 restarts;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69};
Christopher Ferrise01d32f2015-03-31 14:57:48 -0700[diff] [blame]70enum {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]71 IFLA_CAN_UNSPEC,
72 IFLA_CAN_BITTIMING,
73 IFLA_CAN_BITTIMING_CONST,
Christopher Ferrise01d32f2015-03-31 14:57:48 -0700[diff] [blame]74 IFLA_CAN_CLOCK,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]75 IFLA_CAN_STATE,
76 IFLA_CAN_CTRLMODE,
77 IFLA_CAN_RESTART_MS,
Christopher Ferrise01d32f2015-03-31 14:57:48 -0700[diff] [blame]78 IFLA_CAN_RESTART,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 IFLA_CAN_BERR_COUNTER,
80 IFLA_CAN_DATA_BITTIMING,
81 IFLA_CAN_DATA_BITTIMING_CONST,
Christopher Ferris525ce912017-07-26 13:12:53 -0700[diff] [blame]82 IFLA_CAN_TERMINATION,
83 IFLA_CAN_TERMINATION_CONST,
84 IFLA_CAN_BITRATE_CONST,
85 IFLA_CAN_DATA_BITRATE_CONST,
Christopher Ferris76a1d452018-06-27 14:12:29 -0700[diff] [blame]86 IFLA_CAN_BITRATE_MAX,
Christopher Ferrisa4792612022-01-10 13:51:15 -0800[diff] [blame]87 IFLA_CAN_TDC,
Christopher Ferris1ed55342022-03-22 16:06:25 -0700[diff] [blame]88 IFLA_CAN_CTRLMODE_EXT,
Christopher Ferrisa4792612022-01-10 13:51:15 -0800[diff] [blame]89 __IFLA_CAN_MAX,
90 IFLA_CAN_MAX = __IFLA_CAN_MAX - 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]91};
Christopher Ferrisa4792612022-01-10 13:51:15 -0800[diff] [blame]92enum {
93 IFLA_CAN_TDC_UNSPEC,
94 IFLA_CAN_TDC_TDCV_MIN,
95 IFLA_CAN_TDC_TDCV_MAX,
96 IFLA_CAN_TDC_TDCO_MIN,
97 IFLA_CAN_TDC_TDCO_MAX,
98 IFLA_CAN_TDC_TDCF_MIN,
99 IFLA_CAN_TDC_TDCF_MAX,
100 IFLA_CAN_TDC_TDCV,
101 IFLA_CAN_TDC_TDCO,
102 IFLA_CAN_TDC_TDCF,
103 __IFLA_CAN_TDC,
104 IFLA_CAN_TDC_MAX = __IFLA_CAN_TDC - 1
105};
Christopher Ferris1ed55342022-03-22 16:06:25 -0700[diff] [blame]106enum {
107 IFLA_CAN_CTRLMODE_UNSPEC,
108 IFLA_CAN_CTRLMODE_SUPPORTED,
109 __IFLA_CAN_CTRLMODE,
110 IFLA_CAN_CTRLMODE_MAX = __IFLA_CAN_CTRLMODE - 1
111};
Christopher Ferris525ce912017-07-26 13:12:53 -0700[diff] [blame]112#define CAN_TERMINATION_DISABLED 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]113#endif