blob: aa408d80a40c8507d8a363b347ed1e59b1f474cf [file] [log] [blame]
Christopher Ferrisa9750ed2021-05-03 14:02:49 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_ACRN_H
20#define _UAPI_ACRN_H
21#include <linux/types.h>
Christopher Ferrisa9750ed2021-05-03 14:02:49 -070022#define ACRN_IO_REQUEST_MAX 16
23#define ACRN_IOREQ_STATE_PENDING 0
24#define ACRN_IOREQ_STATE_COMPLETE 1
25#define ACRN_IOREQ_STATE_PROCESSING 2
26#define ACRN_IOREQ_STATE_FREE 3
27#define ACRN_IOREQ_TYPE_PORTIO 0
28#define ACRN_IOREQ_TYPE_MMIO 1
29#define ACRN_IOREQ_TYPE_PCICFG 2
30#define ACRN_IOREQ_DIR_READ 0
31#define ACRN_IOREQ_DIR_WRITE 1
32struct acrn_mmio_request {
33 __u32 direction;
34 __u32 reserved;
35 __u64 address;
36 __u64 size;
37 __u64 value;
38};
39struct acrn_pio_request {
40 __u32 direction;
41 __u32 reserved;
42 __u64 address;
43 __u64 size;
44 __u32 value;
45};
46struct acrn_pci_request {
47 __u32 direction;
48 __u32 reserved[3];
49 __u64 size;
50 __u32 value;
51 __u32 bus;
52 __u32 dev;
53 __u32 func;
54 __u32 reg;
55};
56struct acrn_io_request {
57 __u32 type;
58 __u32 completion_polling;
59 __u32 reserved0[14];
60 union {
61 struct acrn_pio_request pio_request;
62 struct acrn_pci_request pci_request;
63 struct acrn_mmio_request mmio_request;
64 __u64 data[8];
65 } reqs;
66 __u32 reserved1;
67 __u32 kernel_handled;
68 __u32 processed;
69} __attribute__((aligned(256)));
70struct acrn_io_request_buffer {
71 union {
72 struct acrn_io_request req_slot[ACRN_IO_REQUEST_MAX];
73 __u8 reserved[4096];
74 };
75};
76struct acrn_ioreq_notify {
77 __u16 vmid;
78 __u16 reserved;
79 __u32 vcpu;
80};
81struct acrn_vm_creation {
82 __u16 vmid;
83 __u16 reserved0;
84 __u16 vcpu_num;
85 __u16 reserved1;
Christopher Ferris8b7fdc92023-02-21 13:36:32 -080086 __u8 uuid[16];
Christopher Ferrisa9750ed2021-05-03 14:02:49 -070087 __u64 vm_flag;
88 __u64 ioreq_buf;
89 __u64 cpu_affinity;
90};
91struct acrn_gp_regs {
92 __le64 rax;
93 __le64 rcx;
94 __le64 rdx;
95 __le64 rbx;
96 __le64 rsp;
97 __le64 rbp;
98 __le64 rsi;
99 __le64 rdi;
100 __le64 r8;
101 __le64 r9;
102 __le64 r10;
103 __le64 r11;
104 __le64 r12;
105 __le64 r13;
106 __le64 r14;
107 __le64 r15;
108};
109struct acrn_descriptor_ptr {
110 __le16 limit;
111 __le64 base;
112 __le16 reserved[3];
113} __attribute__((__packed__));
114struct acrn_regs {
115 struct acrn_gp_regs gprs;
116 struct acrn_descriptor_ptr gdt;
117 struct acrn_descriptor_ptr idt;
118 __le64 rip;
119 __le64 cs_base;
120 __le64 cr0;
121 __le64 cr4;
122 __le64 cr3;
123 __le64 ia32_efer;
124 __le64 rflags;
125 __le64 reserved_64[4];
126 __le32 cs_ar;
127 __le32 cs_limit;
128 __le32 reserved_32[3];
129 __le16 cs_sel;
130 __le16 ss_sel;
131 __le16 ds_sel;
132 __le16 es_sel;
133 __le16 fs_sel;
134 __le16 gs_sel;
135 __le16 ldt_sel;
136 __le16 tr_sel;
137};
138struct acrn_vcpu_regs {
139 __u16 vcpu_id;
140 __u16 reserved[3];
141 struct acrn_regs vcpu_regs;
142};
143#define ACRN_MEM_ACCESS_RIGHT_MASK 0x00000007U
144#define ACRN_MEM_ACCESS_READ 0x00000001U
145#define ACRN_MEM_ACCESS_WRITE 0x00000002U
146#define ACRN_MEM_ACCESS_EXEC 0x00000004U
147#define ACRN_MEM_ACCESS_RWX (ACRN_MEM_ACCESS_READ | ACRN_MEM_ACCESS_WRITE | ACRN_MEM_ACCESS_EXEC)
148#define ACRN_MEM_TYPE_MASK 0x000007C0U
149#define ACRN_MEM_TYPE_WB 0x00000040U
150#define ACRN_MEM_TYPE_WT 0x00000080U
151#define ACRN_MEM_TYPE_UC 0x00000100U
152#define ACRN_MEM_TYPE_WC 0x00000200U
153#define ACRN_MEM_TYPE_WP 0x00000400U
154#define ACRN_MEMMAP_RAM 0
155#define ACRN_MEMMAP_MMIO 1
156struct acrn_vm_memmap {
157 __u32 type;
158 __u32 attr;
159 __u64 user_vm_pa;
160 union {
161 __u64 service_vm_pa;
162 __u64 vma_base;
163 };
164 __u64 len;
165};
166#define ACRN_PTDEV_IRQ_INTX 0
167#define ACRN_PTDEV_IRQ_MSI 1
168#define ACRN_PTDEV_IRQ_MSIX 2
169struct acrn_ptdev_irq {
170 __u32 type;
171 __u16 virt_bdf;
172 __u16 phys_bdf;
173 struct {
174 __u32 virt_pin;
175 __u32 phys_pin;
176 __u32 is_pic_pin;
177 } intx;
178};
179#define ACRN_PTDEV_QUIRK_ASSIGN (1U << 0)
Christopher Ferrisa4792612022-01-10 13:51:15 -0800180#define ACRN_MMIODEV_RES_NUM 3
Christopher Ferrisa9750ed2021-05-03 14:02:49 -0700181#define ACRN_PCI_NUM_BARS 6
182struct acrn_pcidev {
183 __u32 type;
184 __u16 virt_bdf;
185 __u16 phys_bdf;
186 __u8 intr_line;
187 __u8 intr_pin;
188 __u32 bar[ACRN_PCI_NUM_BARS];
189};
Christopher Ferrisa4792612022-01-10 13:51:15 -0800190struct acrn_mmiodev {
191 __u8 name[8];
192 struct {
193 __u64 user_vm_pa;
194 __u64 service_vm_pa;
195 __u64 size;
196 __u64 mem_type;
197 } res[ACRN_MMIODEV_RES_NUM];
198};
199struct acrn_vdev {
200 union {
201 __u64 value;
202 struct {
203 __le16 vendor;
204 __le16 device;
205 __le32 legacy_id;
206 } fields;
207 } id;
208 __u64 slot;
209 __u32 io_addr[ACRN_PCI_NUM_BARS];
210 __u32 io_size[ACRN_PCI_NUM_BARS];
211 __u8 args[128];
212};
Christopher Ferrisa9750ed2021-05-03 14:02:49 -0700213struct acrn_msi_entry {
214 __u64 msi_addr;
215 __u64 msi_data;
216};
217struct acrn_acpi_generic_address {
218 __u8 space_id;
219 __u8 bit_width;
220 __u8 bit_offset;
221 __u8 access_size;
222 __u64 address;
223} __attribute__((__packed__));
224struct acrn_cstate_data {
225 struct acrn_acpi_generic_address cx_reg;
226 __u8 type;
227 __u32 latency;
228 __u64 power;
229};
230struct acrn_pstate_data {
231 __u64 core_frequency;
232 __u64 power;
233 __u64 transition_latency;
234 __u64 bus_master_latency;
235 __u64 control;
236 __u64 status;
237};
238#define PMCMD_TYPE_MASK 0x000000ff
239enum acrn_pm_cmd_type {
240 ACRN_PMCMD_GET_PX_CNT,
241 ACRN_PMCMD_GET_PX_DATA,
242 ACRN_PMCMD_GET_CX_CNT,
243 ACRN_PMCMD_GET_CX_DATA,
244};
245#define ACRN_IOEVENTFD_FLAG_PIO 0x01
246#define ACRN_IOEVENTFD_FLAG_DATAMATCH 0x02
247#define ACRN_IOEVENTFD_FLAG_DEASSIGN 0x04
248struct acrn_ioeventfd {
249 __u32 fd;
250 __u32 flags;
251 __u64 addr;
252 __u32 len;
253 __u32 reserved;
254 __u64 data;
255};
256#define ACRN_IRQFD_FLAG_DEASSIGN 0x01
257struct acrn_irqfd {
258 __s32 fd;
259 __u32 flags;
260 struct acrn_msi_entry msi;
261};
262#define ACRN_IOCTL_TYPE 0xA2
263#define ACRN_IOCTL_CREATE_VM _IOWR(ACRN_IOCTL_TYPE, 0x10, struct acrn_vm_creation)
264#define ACRN_IOCTL_DESTROY_VM _IO(ACRN_IOCTL_TYPE, 0x11)
265#define ACRN_IOCTL_START_VM _IO(ACRN_IOCTL_TYPE, 0x12)
266#define ACRN_IOCTL_PAUSE_VM _IO(ACRN_IOCTL_TYPE, 0x13)
267#define ACRN_IOCTL_RESET_VM _IO(ACRN_IOCTL_TYPE, 0x15)
268#define ACRN_IOCTL_SET_VCPU_REGS _IOW(ACRN_IOCTL_TYPE, 0x16, struct acrn_vcpu_regs)
269#define ACRN_IOCTL_INJECT_MSI _IOW(ACRN_IOCTL_TYPE, 0x23, struct acrn_msi_entry)
270#define ACRN_IOCTL_VM_INTR_MONITOR _IOW(ACRN_IOCTL_TYPE, 0x24, unsigned long)
271#define ACRN_IOCTL_SET_IRQLINE _IOW(ACRN_IOCTL_TYPE, 0x25, __u64)
272#define ACRN_IOCTL_NOTIFY_REQUEST_FINISH _IOW(ACRN_IOCTL_TYPE, 0x31, struct acrn_ioreq_notify)
273#define ACRN_IOCTL_CREATE_IOREQ_CLIENT _IO(ACRN_IOCTL_TYPE, 0x32)
274#define ACRN_IOCTL_ATTACH_IOREQ_CLIENT _IO(ACRN_IOCTL_TYPE, 0x33)
275#define ACRN_IOCTL_DESTROY_IOREQ_CLIENT _IO(ACRN_IOCTL_TYPE, 0x34)
276#define ACRN_IOCTL_CLEAR_VM_IOREQ _IO(ACRN_IOCTL_TYPE, 0x35)
277#define ACRN_IOCTL_SET_MEMSEG _IOW(ACRN_IOCTL_TYPE, 0x41, struct acrn_vm_memmap)
278#define ACRN_IOCTL_UNSET_MEMSEG _IOW(ACRN_IOCTL_TYPE, 0x42, struct acrn_vm_memmap)
279#define ACRN_IOCTL_SET_PTDEV_INTR _IOW(ACRN_IOCTL_TYPE, 0x53, struct acrn_ptdev_irq)
280#define ACRN_IOCTL_RESET_PTDEV_INTR _IOW(ACRN_IOCTL_TYPE, 0x54, struct acrn_ptdev_irq)
281#define ACRN_IOCTL_ASSIGN_PCIDEV _IOW(ACRN_IOCTL_TYPE, 0x55, struct acrn_pcidev)
282#define ACRN_IOCTL_DEASSIGN_PCIDEV _IOW(ACRN_IOCTL_TYPE, 0x56, struct acrn_pcidev)
Christopher Ferrisa4792612022-01-10 13:51:15 -0800283#define ACRN_IOCTL_ASSIGN_MMIODEV _IOW(ACRN_IOCTL_TYPE, 0x57, struct acrn_mmiodev)
284#define ACRN_IOCTL_DEASSIGN_MMIODEV _IOW(ACRN_IOCTL_TYPE, 0x58, struct acrn_mmiodev)
285#define ACRN_IOCTL_CREATE_VDEV _IOW(ACRN_IOCTL_TYPE, 0x59, struct acrn_vdev)
286#define ACRN_IOCTL_DESTROY_VDEV _IOW(ACRN_IOCTL_TYPE, 0x5A, struct acrn_vdev)
Christopher Ferrisa9750ed2021-05-03 14:02:49 -0700287#define ACRN_IOCTL_PM_GET_CPU_STATE _IOWR(ACRN_IOCTL_TYPE, 0x60, __u64)
288#define ACRN_IOCTL_IOEVENTFD _IOW(ACRN_IOCTL_TYPE, 0x70, struct acrn_ioeventfd)
289#define ACRN_IOCTL_IRQFD _IOW(ACRN_IOCTL_TYPE, 0x71, struct acrn_irqfd)
290#endif